Plic: split constants from variables used in config string
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11121b6f4c
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89139a9492
@ -112,7 +112,7 @@ object GenerateConfigString {
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val res = new StringBuilder
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val res = new StringBuilder
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res append "plic {\n"
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res append "plic {\n"
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res append s" priority 0x${plicAddr.toString(16)};\n"
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res append s" priority 0x${plicAddr.toString(16)};\n"
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res append s" pending 0x${(plicAddr + c.plicKey.pendingBase).toString(16)};\n"
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res append s" pending 0x${(plicAddr + PLICConsts.pendingBase).toString(16)};\n"
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res append s" ndevs ${c.plicKey.nDevices};\n"
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res append s" ndevs ${c.plicKey.nDevices};\n"
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res append "};\n"
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res append "};\n"
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res append "rtc {\n"
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res append "rtc {\n"
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@ -28,30 +28,39 @@ class LevelGateway extends Module {
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io.plic.valid := io.interrupt && !inFlight
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io.plic.valid := io.interrupt && !inFlight
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}
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}
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case class PLICConfig(nHartsIn: Int, supervisor: Boolean, nDevices: Int, nPriorities: Int, address: BigInt = 0xC000000) {
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object PLICConsts
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def contextsPerHart = if (supervisor) 2 else 1
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{
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def nHarts = contextsPerHart * nHartsIn
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def context(i: Int, mode: Char) = mode match {
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case 'M' => i * contextsPerHart
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case 'S' => require(supervisor); i * contextsPerHart + 1
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}
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def claimAddr(i: Int, mode: Char) = hartBase + hartOffset(context(i, mode)) + claimOffset
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def threshAddr(i: Int, mode: Char) = hartBase + hartOffset(context(i, mode))
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def enableAddr(i: Int, mode: Char) = enableBase + enableOffset(context(i, mode))
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def size = hartBase + hartOffset(maxHarts)
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def maxDevices = 1023
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def maxDevices = 1023
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def maxHarts = 15872
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def maxHarts = 15872
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def priorityBase = 0x0
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def priorityBase = 0x0
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def pendingBase = 0x1000
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def pendingBase = 0x1000
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def enableBase = 0x2000
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def enableBase = 0x2000
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def hartBase = 0x200000
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def hartBase = 0x200000
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require(hartBase >= enableBase + enableOffset(maxHarts))
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def claimOffset = 4
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def priorityBytes = 4
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def enableOffset(i: Int) = i * ((maxDevices+7)/8)
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def enableOffset(i: Int) = i * ((maxDevices+7)/8)
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def hartOffset(i: Int) = i * 0x1000
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def hartOffset(i: Int) = i * 0x1000
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def claimOffset = 4
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def enableBase(i: Int):Int = enableOffset(i) + enableBase
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def priorityBytes = 4
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def hartBase(i: Int):Int = hartOffset(i) + hartBase
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def size = hartBase(maxHarts)
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require(hartBase >= enableBase(maxHarts))
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}
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case class PLICConfig(nHartsIn: Int, supervisor: Boolean, nDevices: Int, nPriorities: Int) {
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import PLICConsts._
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def contextsPerHart = if (supervisor) 2 else 1
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def nHarts = contextsPerHart * nHartsIn
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def context(i: Int, mode: Char) = mode match {
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case 'M' => i * contextsPerHart
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case 'S' => require(supervisor); i * contextsPerHart + 1
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}
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def claimAddr(i: Int, mode: Char) = hartBase(context(i, mode)) + claimOffset
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def threshAddr(i: Int, mode: Char) = hartBase(context(i, mode))
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def enableAddr(i: Int, mode: Char) = enableBase(context(i, mode))
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require(nDevices <= maxDevices)
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require(nDevices <= maxDevices)
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require(nHarts > 0 && nHarts <= maxHarts)
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require(nHarts > 0 && nHarts <= maxHarts)
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@ -59,8 +68,8 @@ case class PLICConfig(nHartsIn: Int, supervisor: Boolean, nDevices: Int, nPriori
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}
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}
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trait HasPLICParamters {
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trait HasPLICParamters {
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val params: (PLICConfig, Parameters)
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val params: (() => PLICConfig, Parameters)
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val cfg = params._1
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val cfg = params._1 ()
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implicit val p = params._2
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implicit val p = params._2
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}
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}
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@ -109,15 +118,15 @@ trait PLICModule extends Module with HasRegMap with HasPLICParamters {
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}
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}
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def priorityRegField(x: UInt) = if (cfg.nPriorities > 0) RegField(32, x) else RegField.r(32, x)
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def priorityRegField(x: UInt) = if (cfg.nPriorities > 0) RegField(32, x) else RegField.r(32, x)
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val piorityRegFields = Seq(cfg.priorityBase -> priority.map(p => priorityRegField(p)))
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val piorityRegFields = Seq(PLICConsts.priorityBase -> priority.map(p => priorityRegField(p)))
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val pendingRegFields = Seq(cfg.pendingBase -> pending .map(b => RegField.r(1, b)))
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val pendingRegFields = Seq(PLICConsts.pendingBase -> pending .map(b => RegField.r(1, b)))
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val enableRegFields = enables.zipWithIndex.map { case (e, i) =>
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val enableRegFields = enables.zipWithIndex.map { case (e, i) =>
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cfg.enableBase + cfg.enableOffset(i) -> e.map(b => RegField(1, b))
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PLICConsts.enableBase(i) -> e.map(b => RegField(1, b))
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}
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}
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val hartRegFields = Seq.tabulate(cfg.nHarts) { i =>
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val hartRegFields = Seq.tabulate(cfg.nHarts) { i =>
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cfg.hartBase + cfg.hartOffset(i) -> Seq(
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PLICConsts.hartBase(i) -> Seq(
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priorityRegField(threshold(i)),
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priorityRegField(threshold(i)),
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RegField(32,
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RegField(32,
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RegReadFn { valid =>
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RegReadFn { valid =>
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@ -146,7 +155,7 @@ trait PLICModule extends Module with HasRegMap with HasPLICParamters {
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}
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}
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/** Platform-Level Interrupt Controller */
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/** Platform-Level Interrupt Controller */
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class TLPLIC(c: PLICConfig)(implicit val p: Parameters)
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class TLPLIC(c: () => PLICConfig, address: BigInt = 0xC000000)(implicit val p: Parameters)
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extends TLRegisterRouter(c.address, size = c.size, beatBytes = p(rocket.XLen)/8, undefZero = false)(
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extends TLRegisterRouter(address, size = PLICConsts.size, beatBytes = p(rocket.XLen)/8, undefZero = false)(
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new TLRegBundle((c, p), _) with PLICBundle)(
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new TLRegBundle((c, p), _) with PLICBundle)(
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new TLRegModule((c, p), _, _) with PLICModule)
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new TLRegModule((c, p), _, _) with PLICModule)
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