don't disassemble within chisel
This commit is contained in:
Andrew Waterman
parent
f12bbc1e43
commit
88d1c47665
@ -317,10 +317,10 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
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Mux(io.ctrl.sel_pc === PC_PCR, pcr.io.evec,
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Mux(io.ctrl.sel_pc === PC_PCR, pcr.io.evec,
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wb_reg_pc)).toUInt // PC_WB
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wb_reg_pc)).toUInt // PC_WB
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printf("C: %d [%d] pc=[%x] W[r%d=%x] R[r%d=%x] R[r%d=%x] inst=[%x] %s\n",
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printf("C: %d [%d] pc=[%x] W[r%d=%x] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n",
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tsc_reg(32,0), io.ctrl.wb_valid, wb_reg_pc,
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tsc_reg(32,0), io.ctrl.wb_valid, wb_reg_pc,
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Mux(wb_wen, wb_reg_waddr, UInt(0)), wb_wdata,
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Mux(wb_wen, wb_reg_waddr, UInt(0)), wb_wdata,
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wb_reg_inst(26,22), Reg(next=Reg(next=ex_rs1)),
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wb_reg_inst(26,22), Reg(next=Reg(next=ex_rs1)),
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wb_reg_inst(21,17), Reg(next=Reg(next=ex_rs2)),
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wb_reg_inst(21,17), Reg(next=Reg(next=ex_rs2)),
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wb_reg_inst, Disassemble(wb_reg_inst))
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wb_reg_inst, wb_reg_inst)
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}
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}
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@ -192,268 +192,3 @@ object Instructions
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def CUSTOM3_RD_RS1 = Bits("b??????????????????????1101111011")
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def CUSTOM3_RD_RS1 = Bits("b??????????????????????1101111011")
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def CUSTOM3_RD_RS1_RS2 = Bits("b??????????????????????1111111011")
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def CUSTOM3_RD_RS1_RS2 = Bits("b??????????????????????1111111011")
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}
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}
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object Disassemble
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{
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def apply(insn: UInt) = {
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val name :: fmt :: Nil = ListLookup(insn, default, table)
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sprintf("%s %s", name, operands(insn, fmt))
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}
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private def operands(insn: Bits, fmt: Bits): Bits = {
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val x = AVec(Str(" x0"), Str(" ra"), Str(" s0"), Str(" s1"),
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Str(" s2"), Str(" s3"), Str(" s4"), Str(" s5"),
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Str(" s6"), Str(" s7"), Str(" s8"), Str(" s9"),
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Str("s10"), Str("s11"), Str(" sp"), Str(" tp"),
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Str(" v0"), Str(" v1"), Str(" a0"), Str(" a1"),
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Str(" a2"), Str(" a3"), Str(" a4"), Str(" a5"),
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Str(" a6"), Str(" a7"), Str(" t0"), Str(" t1"),
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Str(" t2"), Str(" t3"), Str(" t4"), Str(" t5"))
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val f = AVec(Str(" fs0"), Str(" fs1"), Str(" fs2"), Str(" fs3"),
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Str(" fs4"), Str(" fs5"), Str(" fs6"), Str(" fs7"),
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Str(" fs8"), Str(" fs9"), Str("fs10"), Str("fs11"),
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Str("fs12"), Str("fs13"), Str("fs14"), Str("fs15"),
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Str(" fv0"), Str(" fv1"), Str(" fa0"), Str(" fa1"),
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Str(" fa2"), Str(" fa3"), Str(" fa4"), Str(" fa5"),
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Str(" fa6"), Str(" fa7"), Str(" ft0"), Str(" ft1"),
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Str(" ft2"), Str(" ft3"), Str(" ft4"), Str(" ft5"))
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def hex(x: SInt, plus: Char = ' ') =
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Cat(Mux(x < SInt(0), Str("-0x"), Str(plus + "0x")), Str(x.abs, 16))
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val comma = Str(',')
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val lparen = Str('(')
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val rparen = Str(')')
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val rd = insn(31,27)
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val rs1 = insn(26,22)
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val rs2 = insn(21,17)
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val rs3 = insn(16,12)
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val immv = insn(21,10).toSInt
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val bmmv = Cat(insn(31,27), insn(16,10)).toSInt
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val jmmv = insn(31,7).toSInt
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val imm = hex(Mux(fmt === FMT_B, bmmv << UInt(1),
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Mux(fmt === FMT_I || fmt === FMT_LD || fmt === FMT_FLD, immv,
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Mux(fmt === FMT_ST || fmt === FMT_FST, bmmv,
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SInt(0)))))
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val jmm = hex(jmmv << UInt(1))
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val lmm = Cat(Str("0x"), Str(insn(26,7).toUInt, 16))
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val addr = Cat(comma, imm, lparen, x(rs1), rparen)
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val r0 = x(rd)
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val r1 = Cat(r0, comma, x(rs1))
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val r2 = Cat(r1, comma, x(rs2))
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val f1 = Cat(f(rd), comma, f(rs1))
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val f2 = Cat(f1, comma, f(rs2))
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val f3 = Cat(f2, comma, f(rs3))
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val fx = Cat(f(rd), comma, x(rs1))
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val xf1 = Cat(x(rd), comma, f(rs1))
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val xf2 = Cat(xf1, comma, f(rs2))
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val z = Str(' ')
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val i = Cat(r1, comma, imm)
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val b = Cat(x(rs1), comma, x(rs2), comma, imm)
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val j = jmm
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val l = Cat(x(rd), comma, lmm)
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val ld = Cat(x(rd), addr)
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val st = Cat(x(rs2), addr)
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val fld = Cat(f(rd), addr)
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val fst = Cat(f(rs2), addr)
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val amo = r2
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val opts = Seq(r0, r1, r2, f1, f2, f3, fx, xf1, xf2, z, i, b, j, l, ld, st,
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fld, fst, amo)
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val maxLen = opts.map(_.getWidth).reduce(_ max _)
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val padded = opts.map(x => x.toUInt << UInt(maxLen - x.getWidth))
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AVec(padded)(fmt.toUInt)
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}
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private def FMT_X = Bits("b?????", 5)
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private def FMT_R0 = Bits(0, 5)
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private def FMT_R1 = Bits(1, 5)
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private def FMT_R2 = Bits(2, 5)
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private def FMT_F1 = Bits(3, 5)
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private def FMT_F2 = Bits(4, 5)
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private def FMT_F3 = Bits(5, 5)
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private def FMT_FX = Bits(6, 5)
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private def FMT_XF1 = Bits(7, 5)
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private def FMT_XF2 = Bits(8, 5)
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private def FMT_0 = Bits(9, 5)
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private def FMT_I = Bits(10, 5)
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private def FMT_B = Bits(11, 5)
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private def FMT_J = Bits(12, 5)
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private def FMT_L = Bits(13, 5)
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private def FMT_LD = Bits(14, 5)
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private def FMT_ST = Bits(15, 5)
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private def FMT_FLD = Bits(16, 5)
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private def FMT_FST = Bits(17, 5)
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private def FMT_AMO = Bits(18, 5)
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private def default = List(Str("unknown "), FMT_0)
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import Instructions._
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private def table = Array(
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BNE-> List(Str("bne "), FMT_B),
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BEQ-> List(Str("beq "), FMT_B),
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BLT-> List(Str("blt "), FMT_B),
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BLTU-> List(Str("bltu "), FMT_B),
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BGE-> List(Str("bge "), FMT_B),
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BGEU-> List(Str("bgeu "), FMT_B),
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JAL-> List(Str("jal "), FMT_J),
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JALR-> List(Str("jalr "), FMT_LD),
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AUIPC-> List(Str("auipc "), FMT_L),
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LB-> List(Str("lb "), FMT_LD),
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LH-> List(Str("lh "), FMT_LD),
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LW-> List(Str("lw "), FMT_LD),
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LD-> List(Str("ld "), FMT_LD),
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LBU-> List(Str("lbu "), FMT_LD),
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LHU-> List(Str("lhu "), FMT_LD),
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LWU-> List(Str("lwu "), FMT_LD),
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SB-> List(Str("sb "), FMT_ST),
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SH-> List(Str("sh "), FMT_ST),
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SW-> List(Str("sw "), FMT_ST),
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SD-> List(Str("sd "), FMT_ST),
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AMOADD_W-> List(Str("amoaddw "), FMT_AMO),
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AMOSWAP_W-> List(Str("amoswapw"), FMT_AMO),
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AMOAND_W-> List(Str("amoandw "), FMT_AMO),
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AMOOR_W-> List(Str("amoorw "), FMT_AMO),
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AMOMIN_W-> List(Str("amominw "), FMT_AMO),
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AMOMINU_W-> List(Str("amominuw"), FMT_AMO),
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AMOMAX_W-> List(Str("amomaxw "), FMT_AMO),
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AMOMAXU_W-> List(Str("amomaxuw"), FMT_AMO),
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AMOADD_D-> List(Str("amoaddd "), FMT_AMO),
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AMOSWAP_D-> List(Str("amoswapd"), FMT_AMO),
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AMOAND_D-> List(Str("amoandd "), FMT_AMO),
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AMOOR_D-> List(Str("amoord "), FMT_AMO),
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AMOMIN_D-> List(Str("amomind "), FMT_AMO),
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AMOMINU_D-> List(Str("amominud"), FMT_AMO),
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AMOMAX_D-> List(Str("amomaxd "), FMT_AMO),
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AMOMAXU_D-> List(Str("amomaxud"), FMT_AMO),
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LR_W-> List(Str("lr.w "), FMT_AMO),
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LR_D-> List(Str("lr.d "), FMT_AMO),
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SC_W-> List(Str("sc.w "), FMT_AMO),
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SC_D-> List(Str("sc.d "), FMT_AMO),
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LUI-> List(Str("lui "), FMT_L),
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ADDI-> List(Str("addi "), FMT_I),
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SLTI -> List(Str("slti "), FMT_I),
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SLTIU-> List(Str("sltiu "), FMT_I),
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ANDI-> List(Str("andi "), FMT_I),
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ORI-> List(Str("ori "), FMT_I),
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XORI-> List(Str("xori "), FMT_I),
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SLLI-> List(Str("slli "), FMT_I),
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SRLI-> List(Str("srli "), FMT_I),
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SRAI-> List(Str("srai "), FMT_I),
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ADD-> List(Str("add "), FMT_R2),
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SUB-> List(Str("sub "), FMT_R2),
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SLT-> List(Str("slt "), FMT_R2),
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SLTU-> List(Str("sltu "), FMT_R2),
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AND-> List(Str("and "), FMT_R2),
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OR-> List(Str("or "), FMT_R2),
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XOR-> List(Str("xor "), FMT_R2),
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SLL-> List(Str("sll "), FMT_R2),
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SRL-> List(Str("srl "), FMT_R2),
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SRA-> List(Str("sra "), FMT_R2),
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ADDIW-> List(Str("addiw "), FMT_I),
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SLLIW-> List(Str("slliw "), FMT_I),
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SRLIW-> List(Str("srliw "), FMT_I),
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SRAIW-> List(Str("sraiw "), FMT_I),
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ADDW-> List(Str("addw "), FMT_R2),
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SUBW-> List(Str("subw "), FMT_R2),
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SLLW-> List(Str("sllw "), FMT_R2),
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SRLW-> List(Str("srlw "), FMT_R2),
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SRAW-> List(Str("sraw "), FMT_R2),
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MUL-> List(Str("mul "), FMT_R2),
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MULH-> List(Str("mulh "), FMT_R2),
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MULHU-> List(Str("mulhu "), FMT_R2),
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MULHSU-> List(Str("mulhsu "), FMT_R2),
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MULW-> List(Str("mulw "), FMT_R2),
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DIV-> List(Str("div "), FMT_R2),
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DIVU-> List(Str("divu "), FMT_R2),
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REM-> List(Str("rem "), FMT_R2),
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REMU-> List(Str("remu "), FMT_R2),
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DIVW-> List(Str("divw "), FMT_R2),
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DIVUW-> List(Str("divuw "), FMT_R2),
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REMW-> List(Str("remw "), FMT_R2),
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REMUW-> List(Str("remuw "), FMT_R2),
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SYSCALL-> List(Str("syscall "), FMT_0),
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SETPCR-> List(Str("setpcr "), FMT_I),
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CLEARPCR-> List(Str("clearpcr"), FMT_I),
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ERET-> List(Str("eret "), FMT_0),
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FENCE-> List(Str("fence "), FMT_0),
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FENCE_I-> List(Str("fence.i "), FMT_0),
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MFPCR-> List(Str("mfpcr "), FMT_R2),
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MTPCR-> List(Str("mtpcr "), FMT_R2),
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RDTIME-> List(Str("rdtime "), FMT_R0),
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RDCYCLE-> List(Str("rdcycle "), FMT_R0),
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RDINSTRET-> List(Str("rdinstrt"), FMT_R0),
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FCVT_S_D-> List(Str("fcvt.sd "), FMT_F1),
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FCVT_D_S-> List(Str("fcvt.ds "), FMT_F1),
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FSGNJ_S-> List(Str("fsgnj.s "), FMT_F2),
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FSGNJ_D-> List(Str("fsgnj.d "), FMT_F2),
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FSGNJX_S-> List(Str("fsgnx.s "), FMT_F2),
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FSGNJX_D-> List(Str("fsgnx.d "), FMT_F2),
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FSGNJN_S-> List(Str("fsgnjn.s"), FMT_F2),
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FSGNJN_D-> List(Str("fsgnjn.d"), FMT_F2),
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FMIN_S-> List(Str("fmin.s "), FMT_F2),
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FMIN_D-> List(Str("fmin.d "), FMT_F2),
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FMAX_S-> List(Str("fmax.s "), FMT_F2),
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FMAX_D-> List(Str("fmax.d "), FMT_F2),
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FADD_S-> List(Str("fadd.s "), FMT_F2),
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FADD_D-> List(Str("fadd.d "), FMT_F2),
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FSUB_S-> List(Str("fsub.s "), FMT_F2),
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FSUB_D-> List(Str("fsub.d "), FMT_F2),
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FMUL_S-> List(Str("fmul.s "), FMT_F2),
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FMUL_D-> List(Str("fmul.d "), FMT_F2),
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FMADD_S-> List(Str("fmadd.s "), FMT_F3),
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FMADD_D-> List(Str("fmadd.d "), FMT_F3),
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FMSUB_S-> List(Str("fmsub.s "), FMT_F3),
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FMSUB_D-> List(Str("fmsub.d "), FMT_F3),
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FNMADD_S-> List(Str("fnmadd.s"), FMT_F3),
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FNMADD_D-> List(Str("fnmadd.d"), FMT_F3),
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FNMSUB_S-> List(Str("fnmsub.s"), FMT_F3),
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FNMSUB_D-> List(Str("fnmsub.d"), FMT_F3),
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FMV_X_S-> List(Str("fmv.x.s "), FMT_XF1),
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FMV_X_D-> List(Str("fmv.x.d "), FMT_XF1),
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FCVT_W_S-> List(Str("fcvt.ws "), FMT_XF1),
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FCVT_W_D-> List(Str("fcvt.wd "), FMT_XF1),
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FCVT_WU_S-> List(Str("fcvt.wus"), FMT_XF1),
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FCVT_WU_D-> List(Str("fcvt.wud"), FMT_XF1),
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FCVT_L_S-> List(Str("fcvt.ls "), FMT_XF1),
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FCVT_L_D-> List(Str("fcvt.ld "), FMT_XF1),
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FCVT_LU_S-> List(Str("fcvt.lus"), FMT_XF1),
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FCVT_LU_D-> List(Str("fcvt.lud"), FMT_XF1),
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FEQ_S-> List(Str("feq.s "), FMT_XF2),
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FEQ_D-> List(Str("feq.d "), FMT_XF2),
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FLT_S-> List(Str("flt.s "), FMT_XF2),
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FLT_D-> List(Str("flt.d "), FMT_XF2),
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FLE_S-> List(Str("fle.s "), FMT_XF2),
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FLE_D-> List(Str("fle.d "), FMT_XF2),
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FMV_S_X-> List(Str("fmv.s.x "), FMT_FX),
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FMV_D_X-> List(Str("fmv.d.x "), FMT_FX),
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FCVT_S_W-> List(Str("fcvt.sw "), FMT_FX),
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FCVT_D_W-> List(Str("fcvt.dw "), FMT_FX),
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FCVT_S_WU-> List(Str("fcvt.swu"), FMT_FX),
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FCVT_D_WU-> List(Str("fcvt.dwu"), FMT_FX),
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FCVT_S_L-> List(Str("fcvt.sl "), FMT_FX),
|
|
||||||
FCVT_D_L-> List(Str("fcvt.dl "), FMT_FX),
|
|
||||||
FCVT_S_LU-> List(Str("fcvt.slu"), FMT_FX),
|
|
||||||
FCVT_D_LU-> List(Str("fcvt.dlu"), FMT_FX),
|
|
||||||
FRSR-> List(Str("frsr "), FMT_R0),
|
|
||||||
FSSR-> List(Str("fssr "), FMT_R1),
|
|
||||||
FLW-> List(Str("flw "), FMT_FLD),
|
|
||||||
FLD-> List(Str("fld "), FMT_FLD),
|
|
||||||
FSW-> List(Str("fsw "), FMT_FST),
|
|
||||||
FSD-> List(Str("fsd "), FMT_FST)
|
|
||||||
)
|
|
||||||
}
|
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user