riscv/rocket-chip
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don't disassemble within chisel

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This commit is contained in:
Andrew Waterman
2013-09-15 04:14:45 -07:00
parent f12bbc1e43
commit 88d1c47665
2 changed files with 2 additions and 267 deletions
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4
rocket/src/main/scala/dpath.scala
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@ -317,10 +317,10 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
Mux(io.ctrl.sel_pc === PC_PCR, pcr.io.evec,
wb_reg_pc)).toUInt // PC_WB
printf("C: %d [%d] pc=[%x] W[r%d=%x] R[r%d=%x] R[r%d=%x] inst=[%x] %s\n",
printf("C: %d [%d] pc=[%x] W[r%d=%x] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n",
tsc_reg(32,0), io.ctrl.wb_valid, wb_reg_pc,
Mux(wb_wen, wb_reg_waddr, UInt(0)), wb_wdata,
wb_reg_inst(26,22), Reg(next=Reg(next=ex_rs1)),
wb_reg_inst(21,17), Reg(next=Reg(next=ex_rs2)),
wb_reg_inst, Disassemble(wb_reg_inst))
wb_reg_inst, wb_reg_inst)
}