riscv/rocket-chip
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Merged consts-as-traits

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This commit is contained in:
Henry Cook 2012-10-16 16:32:35 -07:00
commit 88ac5af181
20 changed files with 357 additions and 272 deletions
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72
rocket/src/main/scala/arbiter.scala
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@ -1,10 +1,76 @@
package rocket package rocket
import Chisel._; import Chisel._
import Node._; import Node._
import Constants._; import Constants._
import uncore._ import uncore._
class ioHellaCacheArbiter(n: Int) extends Bundle
{
val requestor = Vec(n) { new ioHellaCache() }.flip
val mem = new ioHellaCache
}
class rocketHellaCacheArbiter(n: Int) extends Component
{
val io = new ioHellaCacheArbiter(n)
require(DCACHE_TAG_BITS >= log2Up(n) + CPU_TAG_BITS)
var req_val = Bool(false)
var req_rdy = io.mem.req.ready
for (i <- 0 until n)
{
io.requestor(i).req.ready := req_rdy
req_val = req_val || io.requestor(i).req.valid
req_rdy = req_rdy && !io.requestor(i).req.valid
}
var req_cmd = io.requestor(n-1).req.bits.cmd
var req_type = io.requestor(n-1).req.bits.typ
var req_idx = io.requestor(n-1).req.bits.idx
var req_ppn = io.requestor(n-1).req.bits.ppn
var req_data = io.requestor(n-1).req.bits.data
var req_kill = io.requestor(n-1).req.bits.kill
var req_tag = io.requestor(n-1).req.bits.tag
for (i <- n-1 to 0 by -1)
{
val r = io.requestor(i).req
req_cmd = Mux(r.valid, r.bits.cmd, req_cmd)
req_type = Mux(r.valid, r.bits.typ, req_type)
req_idx = Mux(r.valid, r.bits.idx, req_idx)
req_ppn = Mux(Reg(r.valid), r.bits.ppn, req_ppn)
req_data = Mux(Reg(r.valid), r.bits.data, req_data)
req_kill = Mux(Reg(r.valid), r.bits.kill, req_kill)
req_tag = Mux(r.valid, Cat(r.bits.tag, UFix(i, log2Up(n))), req_tag)
}
io.mem.req.valid := req_val
io.mem.req.bits.cmd := req_cmd
io.mem.req.bits.typ := req_type
io.mem.req.bits.idx := req_idx
io.mem.req.bits.ppn := req_ppn
io.mem.req.bits.data := req_data
io.mem.req.bits.kill := req_kill
io.mem.req.bits.tag := req_tag
for (i <- 0 until n)
{
val r = io.requestor(i).resp
val x = io.requestor(i).xcpt
val tag_hit = io.mem.resp.bits.tag(log2Up(n)-1,0) === UFix(i)
x.ma.ld := io.mem.xcpt.ma.ld && Reg(io.requestor(i).req.valid)
x.ma.st := io.mem.xcpt.ma.st && Reg(io.requestor(i).req.valid)
r.valid := io.mem.resp.valid && tag_hit
r.bits.miss := io.mem.resp.bits.miss && tag_hit
r.bits.nack := io.mem.resp.bits.nack && Reg(io.requestor(i).req.valid)
r.bits.replay := io.mem.resp.bits.replay && tag_hit
r.bits.data := io.mem.resp.bits.data
r.bits.data_subword := io.mem.resp.bits.data_subword
r.bits.typ := io.mem.resp.bits.typ
r.bits.tag := io.mem.resp.bits.tag >> UFix(log2Up(n))
}
}
class ioUncachedRequestor extends Bundle { class ioUncachedRequestor extends Bundle {
val xact_init = (new FIFOIO) { new TransactionInit } val xact_init = (new FIFOIO) { new TransactionInit }
val xact_abort = (new FIFOIO) { new TransactionAbort }.flip val xact_abort = (new FIFOIO) { new TransactionAbort }.flip

56
rocket/src/main/scala/config.scala Normal file
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@ -0,0 +1,56 @@
package rocket
package config
import java.io.File
import java.io.FileInputStream
import java.util.Properties
import scala.util.{Properties => SProperties}
class Config(props: Properties) {
private val msg = "Configuration is missing requested parameter "
def getInt(name: String): Int = Option(props.getProperty(name).toInt).getOrElse(sys.error(msg+name))
def getString(name: String): String = Option(props.getProperty(name)).getOrElse(sys.error(msg+name))
def getBoolean(name: String): Boolean = Option(props.getProperty(name).toBoolean).getOrElse(sys.error(msg+name))
def apply(name: String): Int = getInt(name)
}
object Config {
lazy val internal_config = getConfig()
def apply(name: String) = internal_config(name)
private def getConfig(): Config = {
val filePath0 =
SProperties
.envOrNone("ROCKET_CONFIG")
.orElse(SProperties.propOrNone("rocket.config"))
if (filePath0.isEmpty)
Console.err.println("""
| WARNING: Could not find configuration file to load.
| Options are:
| (1) Set environmental variable ROCKET_CONFIG to the config file path
| (2) Set system property rocket.config to the config file path
| Using default values for config.
""".stripMargin)
val filePath =
filePath0.flatMap(fp => {
val f = new File(fp)
if (!f.isFile) {
Console.err.println("""
| WARNING: File '%s' is not a valid file path
| Using default values for config
""".format(fp).stripMargin)
None
} else Some(fp)
})
val props = new Properties()
filePath.map(fp => props.load(new FileInputStream(fp)))
new Config(props)
}
}

99
rocket/src/main/scala/consts.scala
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@ -1,21 +1,20 @@
package rocket package rocket
package constants
import Chisel._ import Chisel._
import scala.math._ import scala.math._
object Constants abstract trait TileConfigConstants {
{ def HAVE_RVC: Boolean
val NTILES = 1 def HAVE_FPU: Boolean
val HAVE_RVC = false def HAVE_VEC: Boolean
val HAVE_FPU = true val FPU_N = UFix(0, 1)
val HAVE_VEC = false val FPU_Y = if (HAVE_FPU) UFix(1, 1) else FPU_N
val VEC_N = UFix(0, 1);
val MAX_THREADS = val VEC_Y = if (HAVE_VEC) UFix(1, 1) else VEC_N
hwacha.Constants.NUM_PVFB * hwacha.Constants.WIDTH_PVFB / hwacha.Constants.SZ_BANK }
val HTIF_WIDTH = 16
val MEM_BACKUP_WIDTH = HTIF_WIDTH
trait ScalarOpConstants {
val BR_X = Bits("b???", 3) val BR_X = Bits("b???", 3)
val BR_EQ = UFix(0, 3) val BR_EQ = UFix(0, 3)
val BR_NE = UFix(1, 3) val BR_NE = UFix(1, 3)
@ -71,7 +70,9 @@ object Constants
val DW_XPR = Y val DW_XPR = Y
val RA = UFix(1, 5); val RA = UFix(1, 5);
}
trait MemoryOpConstants {
val MT_X = Bits("b???", 3); val MT_X = Bits("b???", 3);
val MT_B = Bits("b000", 3); val MT_B = Bits("b000", 3);
val MT_H = Bits("b001", 3); val MT_H = Bits("b001", 3);
@ -98,7 +99,9 @@ object Constants
val M_XA_MAX = Bits("b1101", 4); val M_XA_MAX = Bits("b1101", 4);
val M_XA_MINU = Bits("b1110", 4); val M_XA_MINU = Bits("b1110", 4);
val M_XA_MAXU = Bits("b1111", 4); val M_XA_MAXU = Bits("b1111", 4);
}
trait PCRConstants {
val PCR_X = Bits("b???", 3) val PCR_X = Bits("b???", 3)
val PCR_N = Bits(0,3) val PCR_N = Bits(0,3)
val PCR_F = Bits(1,3) // mfpcr val PCR_F = Bits(1,3) // mfpcr
@ -143,71 +146,42 @@ object Constants
val SR_VM = 8 // VM enable val SR_VM = 8 // VM enable
val SR_IM = 16 // interrupt mask val SR_IM = 16 // interrupt mask
val SR_IM_WIDTH = 8 val SR_IM_WIDTH = 8
}
trait InterruptConstants {
val CAUSE_INTERRUPT = 32 val CAUSE_INTERRUPT = 32
val IRQ_IPI = 5 val IRQ_IPI = 5
val IRQ_TIMER = 7 val IRQ_TIMER = 7
}
val PADDR_BITS = 40; abstract trait RocketDcacheConstants extends ArbiterConstants with uncore.constants.AddressConstants {
val VADDR_BITS = 43;
val PGIDX_BITS = 13;
val PPN_BITS = PADDR_BITS-PGIDX_BITS;
val VPN_BITS = VADDR_BITS-PGIDX_BITS;
val ASID_BITS = 7;
val PERM_BITS = 6;
// rocketNBDCache parameters
val INST_BITS = 32 val INST_BITS = 32
val DCACHE_PORTS = 3
val CPU_DATA_BITS = 64; val CPU_DATA_BITS = 64;
val CPU_TAG_BITS = 9; val CPU_TAG_BITS = 9;
val DCACHE_TAG_BITS = log2Up(DCACHE_PORTS) + CPU_TAG_BITS val DCACHE_TAG_BITS = log2Up(DCACHE_PORTS) + CPU_TAG_BITS
val OFFSET_BITS = 6; // log2(cache line size in bytes) val LG_REFILL_WIDTH = 4; // log2(cache bus width in bytes)
val NMSHR = if (HAVE_VEC) 4 else 2 // number of primary misses val NMSHR = if (HAVE_VEC) 4 else 2 // number of primary misses
require(log2Up(NMSHR)+3 <= uncore.Constants.TILE_XACT_ID_BITS)
val NRPQ = 16; // number of secondary misses val NRPQ = 16; // number of secondary misses
val NSDQ = 17; // number of secondary stores/AMOs val NSDQ = 17; // number of secondary stores/AMOs
val LG_REFILL_WIDTH = 4; // log2(cache bus width in bytes) val OFFSET_BITS = 6; // log2(cache line size in bytes)
require(OFFSET_BITS == log2Up(uncore.Constants.CACHE_DATA_SIZE_IN_BYTES))
require(OFFSET_BITS <= uncore.Constants.X_INIT_WRITE_MASK_BITS)
require(log2Up(OFFSET_BITS) <= uncore.Constants.X_INIT_SUBWORD_ADDR_BITS)
val IDX_BITS = 7; val IDX_BITS = 7;
val TAG_BITS = PADDR_BITS - OFFSET_BITS - IDX_BITS; val TAG_BITS = PADDR_BITS - OFFSET_BITS - IDX_BITS;
val NWAYS = 4 val NWAYS = 4
require(IDX_BITS+OFFSET_BITS <= PGIDX_BITS); require(IDX_BITS+OFFSET_BITS <= PGIDX_BITS);
}
// coherence parameters trait TLBConstants {
val ENABLE_SHARING = true
val ENABLE_CLEAN_EXCLUSIVE = true
val COHERENCE_DATA_BITS = (1 << OFFSET_BITS)*8
val TILE_ID_BITS = log2Up(NTILES)+1
val TILE_XACT_ID_BITS = log2Up(NMSHR)+3
val NGLOBAL_XACTS = 8
val GLOBAL_XACT_ID_BITS = log2Up(NGLOBAL_XACTS)
val X_INIT_TYPE_MAX_BITS = 2
val X_INIT_WRITE_MASK_BITS = OFFSET_BITS
val X_INIT_SUBWORD_ADDR_BITS = log2Up(OFFSET_BITS)
val X_INIT_ATOMIC_OP_BITS = 4
val X_REP_TYPE_MAX_BITS = 3
val P_REQ_TYPE_MAX_BITS = 2
val P_REP_TYPE_MAX_BITS = 3
// external memory interface
val MEM_TAG_BITS = max(TILE_XACT_ID_BITS, GLOBAL_XACT_ID_BITS)
val MEM_DATA_BITS = 128
val REFILL_CYCLES = (1 << OFFSET_BITS)*8/MEM_DATA_BITS
val BTB_ENTRIES = 8 val BTB_ENTRIES = 8
val ITLB_ENTRIES = 8 val ITLB_ENTRIES = 8
val DTLB_ENTRIES = 16 val DTLB_ENTRIES = 16
val VITLB_ENTRIES = 4 val VITLB_ENTRIES = 4
}
val START_ADDR = 0x2000; trait VectorOpConstants {
val FPU_N = UFix(0, 1);
val FPU_Y = if (HAVE_FPU) UFix(1, 1) else FPU_N;
val VEC_N = UFix(0, 1);
val VEC_Y = if (HAVE_VEC) UFix(1, 1) else VEC_N;
val VEC_X = Bits("b??", 2).toUFix val VEC_X = Bits("b??", 2).toUFix
val VEC_FN_N = UFix(0, 2) val VEC_FN_N = UFix(0, 2)
val VEC_VL = UFix(1, 2) val VEC_VL = UFix(1, 2)
@ -230,12 +204,21 @@ object Constants
val VIMM2_RS2 = UFix(0, 1) val VIMM2_RS2 = UFix(0, 1)
val VIMM2_ALU = UFix(1, 1) val VIMM2_ALU = UFix(1, 1)
val VIMM2_X = UFix(0, 1) val VIMM2_X = UFix(0, 1)
}
abstract trait ArbiterConstants extends TileConfigConstants {
val DTLB_PORTS = 3
val DTLB_CPU = 0 val DTLB_CPU = 0
val DTLB_VEC = 1 val DTLB_VEC = 1
val DTLB_VPF = 2 val DTLB_VPF = 2
val DMEM_CPU = 0 val DCACHE_PORTS = 3
val DMEM_PTW = 1 val DCACHE_CPU = 0
val DMEM_VU = 2 val DCACHE_PTW = 1
val DCACHE_VU = 2
val DMEM_PORTS = if (HAVE_VEC) 3 else 2
val DMEM_DCACHE = 0
val DMEM_ICACHE = 1
val DMEM_VICACHE = 2
} }

76
rocket/src/main/scala/cpu.scala
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@ -1,11 +1,11 @@
package rocket package rocket
import Chisel._; import Chisel._
import Node._; import Node._
import Constants._; import Constants._
import hwacha._ import hwacha._
class ioRocket extends Bundle() class ioRocket(implicit conf: RocketConfiguration) extends Bundle
{ {
val host = new ioHTIF val host = new ioHTIF
val imem = new IOCPUFrontend val imem = new IOCPUFrontend
@ -13,12 +13,12 @@ class ioRocket extends Bundle()
val dmem = new ioHellaCache val dmem = new ioHellaCache
} }
class rocketProc extends Component class rocketProc(implicit conf: RocketConfiguration) extends Component
{ {
val io = new ioRocket val io = new ioRocket
val ctrl = new rocketCtrl(); val ctrl = new rocketCtrl
val dpath = new rocketDpath(); val dpath = new rocketDpath
val dtlb = new rocketTLB(DTLB_ENTRIES); val dtlb = new rocketTLB(DTLB_ENTRIES);
val ptw = new rocketPTW(if (HAVE_VEC) 3 else 2) val ptw = new rocketPTW(if (HAVE_VEC) 3 else 2)
@ -29,8 +29,8 @@ class rocketProc extends Component
{ {
vu = new vu() vu = new vu()
// cpu, vector prefetch, and vector use the DTLB // cpu, vector prefetch, and vector use the DTLB
val dtlbarb = new RRArbiter(3)({new ioDTLB_CPU_req_bundle()}) val dtlbarb = new RRArbiter(DTLB_PORTS)({new ioDTLB_CPU_req_bundle()})
val dtlbchosen = Reg(resetVal=Bits(DTLB_CPU,log2Up(3))) val dtlbchosen = Reg(resetVal=Bits(DTLB_CPU,log2Up(DTLB_PORTS)))
when( dtlb.io.cpu_req.ready && dtlbarb.io.out.valid ) { dtlbchosen := dtlbarb.io.chosen } when( dtlb.io.cpu_req.ready && dtlbarb.io.out.valid ) { dtlbchosen := dtlbarb.io.chosen }
// tlb respones come out a cycle later // tlb respones come out a cycle later
@ -85,15 +85,15 @@ class rocketProc extends Component
dtlb.io.invalidate := dpath.io.ptbr_wen dtlb.io.invalidate := dpath.io.ptbr_wen
dtlb.io.status := dpath.io.ctrl.status dtlb.io.status := dpath.io.ctrl.status
arb.io.requestor(DMEM_CPU).req.bits.ppn := dtlb.io.cpu_resp.ppn arb.io.requestor(DCACHE_CPU).req.bits.ppn := dtlb.io.cpu_resp.ppn
ctrl.io.dmem.req.ready := dtlb.io.cpu_req.ready && arb.io.requestor(DMEM_CPU).req.ready ctrl.io.dmem.req.ready := dtlb.io.cpu_req.ready && arb.io.requestor(DCACHE_CPU).req.ready
// connect page table walker to TLBs, page table base register (from PCR) // connect page table walker to TLBs, page table base register (from PCR)
// and D$ arbiter (selects between requests from pipeline and PTW, PTW has priority) // and D$ arbiter (selects between requests from pipeline and PTW, PTW has priority)
ptw.io.requestor(0) <> io.imem.ptw ptw.io.requestor(0) <> io.imem.ptw
ptw.io.requestor(1) <> dtlb.io.ptw ptw.io.requestor(1) <> dtlb.io.ptw
ptw.io.ptbr := dpath.io.ptbr; ptw.io.ptbr := dpath.io.ptbr;
arb.io.requestor(DMEM_PTW) <> ptw.io.mem arb.io.requestor(DCACHE_PTW) <> ptw.io.mem
arb.io.mem <> io.dmem arb.io.mem <> io.dmem
ctrl.io.dpath <> dpath.io.ctrl; ctrl.io.dpath <> dpath.io.ctrl;
@ -107,17 +107,17 @@ class rocketProc extends Component
// connect arbiter to ctrl+dpath+DTLB // connect arbiter to ctrl+dpath+DTLB
//TODO: views on nested bundles? //TODO: views on nested bundles?
arb.io.requestor(DMEM_CPU).resp <> ctrl.io.dmem.resp arb.io.requestor(DCACHE_CPU).resp <> ctrl.io.dmem.resp
arb.io.requestor(DMEM_CPU).xcpt <> ctrl.io.dmem.xcpt arb.io.requestor(DCACHE_CPU).xcpt <> ctrl.io.dmem.xcpt
arb.io.requestor(DMEM_CPU).resp <> dpath.io.dmem.resp arb.io.requestor(DCACHE_CPU).resp <> dpath.io.dmem.resp
arb.io.requestor(DMEM_CPU).req.valid := ctrl.io.dmem.req.valid arb.io.requestor(DCACHE_CPU).req.valid := ctrl.io.dmem.req.valid
ctrl.io.dmem.req.ready := arb.io.requestor(DMEM_CPU).req.ready ctrl.io.dmem.req.ready := arb.io.requestor(DCACHE_CPU).req.ready
arb.io.requestor(DMEM_CPU).req.bits.kill := ctrl.io.dmem.req.bits.kill arb.io.requestor(DCACHE_CPU).req.bits.kill := ctrl.io.dmem.req.bits.kill
arb.io.requestor(DMEM_CPU).req.bits.cmd := ctrl.io.dmem.req.bits.cmd arb.io.requestor(DCACHE_CPU).req.bits.cmd := ctrl.io.dmem.req.bits.cmd
arb.io.requestor(DMEM_CPU).req.bits.typ := ctrl.io.dmem.req.bits.typ arb.io.requestor(DCACHE_CPU).req.bits.typ := ctrl.io.dmem.req.bits.typ
arb.io.requestor(DMEM_CPU).req.bits.idx := dpath.io.dmem.req.bits.idx arb.io.requestor(DCACHE_CPU).req.bits.idx := dpath.io.dmem.req.bits.idx
arb.io.requestor(DMEM_CPU).req.bits.tag := dpath.io.dmem.req.bits.tag arb.io.requestor(DCACHE_CPU).req.bits.tag := dpath.io.dmem.req.bits.tag
arb.io.requestor(DMEM_CPU).req.bits.data := dpath.io.dmem.req.bits.data arb.io.requestor(DCACHE_CPU).req.bits.data := dpath.io.dmem.req.bits.data
var fpu: rocketFPU = null var fpu: rocketFPU = null
if (HAVE_FPU) if (HAVE_FPU)
@ -202,21 +202,21 @@ class rocketProc extends Component
storegen.io.typ := vu.io.dmem_req.bits.typ storegen.io.typ := vu.io.dmem_req.bits.typ
storegen.io.din := vu.io.dmem_req.bits.data storegen.io.din := vu.io.dmem_req.bits.data
arb.io.requestor(DMEM_VU).req.valid := vu.io.dmem_req.valid arb.io.requestor(DCACHE_VU).req.valid := vu.io.dmem_req.valid
arb.io.requestor(DMEM_VU).req.bits.kill := vu.io.dmem_req.bits.kill arb.io.requestor(DCACHE_VU).req.bits.kill := vu.io.dmem_req.bits.kill
arb.io.requestor(DMEM_VU).req.bits.cmd := vu.io.dmem_req.bits.cmd arb.io.requestor(DCACHE_VU).req.bits.cmd := vu.io.dmem_req.bits.cmd
arb.io.requestor(DMEM_VU).req.bits.typ := vu.io.dmem_req.bits.typ arb.io.requestor(DCACHE_VU).req.bits.typ := vu.io.dmem_req.bits.typ
arb.io.requestor(DMEM_VU).req.bits.idx := vu.io.dmem_req.bits.idx arb.io.requestor(DCACHE_VU).req.bits.idx := vu.io.dmem_req.bits.idx
arb.io.requestor(DMEM_VU).req.bits.ppn := Reg(vu.io.dmem_req.bits.ppn) arb.io.requestor(DCACHE_VU).req.bits.ppn := Reg(vu.io.dmem_req.bits.ppn)
arb.io.requestor(DMEM_VU).req.bits.data := Reg(storegen.io.dout) arb.io.requestor(DCACHE_VU).req.bits.data := Reg(storegen.io.dout)
arb.io.requestor(DMEM_VU).req.bits.tag := vu.io.dmem_req.bits.tag arb.io.requestor(DCACHE_VU).req.bits.tag := vu.io.dmem_req.bits.tag
vu.io.dmem_req.ready := arb.io.requestor(DMEM_VU).req.ready vu.io.dmem_req.ready := arb.io.requestor(DCACHE_VU).req.ready
vu.io.dmem_resp.valid := Reg(arb.io.requestor(DMEM_VU).resp.valid) vu.io.dmem_resp.valid := Reg(arb.io.requestor(DCACHE_VU).resp.valid)
vu.io.dmem_resp.bits.nack := arb.io.requestor(DMEM_VU).resp.bits.nack vu.io.dmem_resp.bits.nack := arb.io.requestor(DCACHE_VU).resp.bits.nack
vu.io.dmem_resp.bits.data := arb.io.requestor(DMEM_VU).resp.bits.data_subword vu.io.dmem_resp.bits.data := arb.io.requestor(DCACHE_VU).resp.bits.data_subword
vu.io.dmem_resp.bits.tag := Reg(arb.io.requestor(DMEM_VU).resp.bits.tag) vu.io.dmem_resp.bits.tag := Reg(arb.io.requestor(DCACHE_VU).resp.bits.tag)
vu.io.dmem_resp.bits.typ := Reg(arb.io.requestor(DMEM_VU).resp.bits.typ) vu.io.dmem_resp.bits.typ := Reg(arb.io.requestor(DCACHE_VU).resp.bits.typ)
// share vector integer multiplier with rocket // share vector integer multiplier with rocket
dpath.io.vec_imul_req <> vu.io.cp_imul_req dpath.io.vec_imul_req <> vu.io.cp_imul_req
@ -228,7 +228,7 @@ class rocketProc extends Component
} }
else else
{ {
arb.io.requestor(DMEM_VU).req.valid := Bool(false) arb.io.requestor(DCACHE_VU).req.valid := Bool(false)
if (HAVE_FPU) if (HAVE_FPU)
{ {
fpu.io.sfma.valid := Bool(false) fpu.io.sfma.valid := Bool(false)

34
rocket/src/main/scala/ctrl.scala
View File

@ -1,8 +1,7 @@
package rocket package rocket
import Chisel._ import Chisel._
import Node._; import Node._
import Constants._ import Constants._
import Instructions._ import Instructions._
import hwacha._ import hwacha._
@ -88,19 +87,24 @@ class ioCtrlAll extends Bundle()
val vec_iface = new ioCtrlVecInterface() val vec_iface = new ioCtrlVecInterface()
} }
object rocketCtrlDecode abstract trait rocketCtrlDecodeConstants
{ {
val xpr64 = Y; val xpr64 = Y;
val decode_default = val decode_default =
// jalr eret // jalr eret
// fp_val | renx2 div_val | syscall // fp_val | renx2 div_val | syscall
// | vec_val | | renx1 mem_val mul_val | wen pcr | | privileged // | vec_val | | renx1 mem_val mul_val | wen pcr | | privileged
// val | | brtype | | | s_alu2 dw alu | mem_cmd mem_type| mul_fn | | s_wa s_wb | sync | | | replay_next // val | | brtype | | | s_alu2 dw alu | mem_cmd mem_type| mul_fn | | s_wa s_wb | sync | | | replay_next
// | | | | | | | | | | | | | | | | | | | | | | | | | // | | | | | | | | | | | | | | | | | | | | | | | | |
List(N, X,X,BR_X, X,X,X,A2_X, DW_X, FN_X, N,M_X, MT_X, X,MUL_X, X,X,WA_X, WB_X, PCR_X,SYNC_X,X,X,X,X) List(N, X,X,BR_X, X,X,X,A2_X, DW_X, FN_X, N,M_X, MT_X, X,MUL_X, X,X,WA_X, WB_X, PCR_X,SYNC_X,X,X,X,X)
val xdecode = Array( val table: Array[(Bits, List[Bits])]
}
object rocketCtrlXDecode extends rocketCtrlDecodeConstants
{
val table = Array(
// jalr eret // jalr eret
// fp_val | renx2 div_val | syscall // fp_val | renx2 div_val | syscall
// | vec_val | | renx1 mem_val mul_val | wen pcr | | privileged // | vec_val | | renx1 mem_val mul_val | wen pcr | | privileged
@ -207,8 +211,11 @@ object rocketCtrlDecode
RDTIME-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_XPR,FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_TSC,PCR_N,SYNC_N,N,N,N,N), RDTIME-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_XPR,FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_TSC,PCR_N,SYNC_N,N,N,N,N),
RDCYCLE-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_XPR,FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_TSC,PCR_N,SYNC_N,N,N,N,N), RDCYCLE-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_XPR,FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_TSC,PCR_N,SYNC_N,N,N,N,N),
RDINSTRET-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_XPR,FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_IRT,PCR_N,SYNC_N,N,N,N,N)) RDINSTRET-> List(Y, N,N,BR_N, N,N,N,A2_X, DW_XPR,FN_X, N,M_X, MT_X, N,MUL_X, N,Y,WA_RD,WB_IRT,PCR_N,SYNC_N,N,N,N,N))
}
val fdecode = Array( object rocketCtrlFDecode extends rocketCtrlDecodeConstants
{
val table = Array(
// jalr eret // jalr eret
// fp_val | renx2 div_val | syscall // fp_val | renx2 div_val | syscall
// | vec_val | | renx1 mem_val mul_val | wen pcr | | privileged // | vec_val | | renx1 mem_val mul_val | wen pcr | | privileged
@ -272,8 +279,11 @@ object rocketCtrlDecode
FLD-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), FLD-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_D, N,MUL_X, N,N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N),
FSW-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_BTYPE,DW_XPR,FN_ADD, Y,M_XWR, MT_W, N,MUL_X, N,N,WA_X, WB_ALU,PCR_N,SYNC_N,N,N,N,N), FSW-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_BTYPE,DW_XPR,FN_ADD, Y,M_XWR, MT_W, N,MUL_X, N,N,WA_X, WB_ALU,PCR_N,SYNC_N,N,N,N,N),
FSD-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_BTYPE,DW_XPR,FN_ADD, Y,M_XWR, MT_D, N,MUL_X, N,N,WA_X, WB_ALU,PCR_N,SYNC_N,N,N,N,N)) FSD-> List(FPU_Y,Y,N,BR_N, N,N,Y,A2_BTYPE,DW_XPR,FN_ADD, Y,M_XWR, MT_D, N,MUL_X, N,N,WA_X, WB_ALU,PCR_N,SYNC_N,N,N,N,N))
}
val vdecode = Array( object rocketCtrlVDecode extends rocketCtrlDecodeConstants
{
val table = Array(
// jalr eret // jalr eret
// fp_val | renx2 div_val | syscall // fp_val | renx2 div_val | syscall
// | vec_val | | renx1 mem_val mul_val | wen pcr | | privileged // | vec_val | | renx1 mem_val mul_val | wen pcr | | privileged
@ -332,11 +342,11 @@ class rocketCtrl extends Component
{ {
val io = new ioCtrlAll(); val io = new ioCtrlAll();
var decode_table = rocketCtrlDecode.xdecode var decode_table = rocketCtrlXDecode.table
if (HAVE_FPU) decode_table ++= rocketCtrlDecode.fdecode if (HAVE_FPU) decode_table ++= rocketCtrlFDecode.table
if (HAVE_VEC) decode_table ++= rocketCtrlDecode.vdecode if (HAVE_VEC) decode_table ++= rocketCtrlVDecode.table
val cs = DecodeLogic(io.dpath.inst, rocketCtrlDecode.decode_default, decode_table) val cs = DecodeLogic(io.dpath.inst, rocketCtrlXDecode.decode_default, decode_table)
val id_int_val :: id_fp_val :: id_vec_val :: id_br_type :: id_jalr :: id_renx2 :: id_renx1 :: id_sel_alu2 :: id_fn_dw :: id_fn_alu :: cs0 = cs val id_int_val :: id_fp_val :: id_vec_val :: id_br_type :: id_jalr :: id_renx2 :: id_renx1 :: id_sel_alu2 :: id_fn_dw :: id_fn_alu :: cs0 = cs
val id_mem_val :: id_mem_cmd :: id_mem_type :: id_mul_val :: id_mul_fn :: id_div_val :: id_wen :: id_sel_wa :: id_sel_wb :: cs1 = cs0 val id_mem_val :: id_mem_cmd :: id_mem_type :: id_mul_val :: id_mul_fn :: id_div_val :: id_wen :: id_sel_wa :: id_sel_wb :: cs1 = cs0

2
rocket/src/main/scala/ctrl_util.scala
View File

@ -1,7 +1,7 @@
package rocket package rocket
import Chisel._ import Chisel._
import Node._; import Node._
class rocketCtrlSboard(entries: Int, nread: Int, nwrite: Int) extends Component class rocketCtrlSboard(entries: Int, nread: Int, nwrite: Int) extends Component
{ {

11
rocket/src/main/scala/dpath.scala
View File

@ -1,15 +1,14 @@
package rocket package rocket
import Chisel._ import Chisel._
import Node._; import Node._
import Constants._ import Constants._
import Instructions._ import Instructions._
import hwacha._ import hwacha._
class ioDpathAll extends Bundle() class ioDpathAll(implicit conf: RocketConfiguration) extends Bundle
{ {
val host = new ioHTIF(); val host = new ioHTIF
val ctrl = new ioCtrlDpath().flip val ctrl = new ioCtrlDpath().flip
val dmem = new ioHellaCache val dmem = new ioHellaCache
val dtlb = new ioDTLB_CPU_req_bundle().asOutput() val dtlb = new ioDTLB_CPU_req_bundle().asOutput()
@ -23,7 +22,7 @@ class ioDpathAll extends Bundle()
val vec_imul_resp = Bits(INPUT, hwacha.Constants.SZ_XLEN) val vec_imul_resp = Bits(INPUT, hwacha.Constants.SZ_XLEN)
} }
class rocketDpath extends Component class rocketDpath(implicit conf: RocketConfiguration) extends Component
{ {
val io = new ioDpathAll(); val io = new ioDpathAll();
@ -48,7 +47,7 @@ class rocketDpath extends Component
val ex_reg_ctrl_fn_dw = Reg() { UFix() }; val ex_reg_ctrl_fn_dw = Reg() { UFix() };
val ex_reg_ctrl_fn_alu = Reg() { UFix() }; val ex_reg_ctrl_fn_alu = Reg() { UFix() };
val ex_reg_ctrl_sel_wb = Reg() { UFix() }; val ex_reg_ctrl_sel_wb = Reg() { UFix() };
val ex_wdata = Bits(); val ex_wdata = Bits()
// memory definitions // memory definitions
val mem_reg_pc = Reg() { UFix() }; val mem_reg_pc = Reg() { UFix() };

3
rocket/src/main/scala/dpath_alu.scala
View File

@ -1,8 +1,7 @@
package rocket package rocket
import Chisel._ import Chisel._
import Node._; import Node._
import Constants._ import Constants._
import Instructions._ import Instructions._

16
rocket/src/main/scala/dpath_util.scala
View File

@ -1,9 +1,9 @@
package rocket package rocket
import Chisel._; import Chisel._
import Node._; import Node._
import Constants._; import Constants._
import scala.math._; import scala.math._
class ioDpathBTB extends Bundle() class ioDpathBTB extends Bundle()
{ {
@ -53,9 +53,9 @@ class rocketDpathBTB(entries: Int) extends Component
io.target := Mux1H(hits, targets) io.target := Mux1H(hits, targets)
} }
class ioDpathPCR extends Bundle() class ioDpathPCR(implicit conf: RocketConfiguration) extends Bundle
{ {
val host = new ioHTIF() val host = new ioHTIF
val r = new ioReadPort(); val r = new ioReadPort();
val w = new ioWritePort(); val w = new ioWritePort();
@ -82,9 +82,9 @@ class ioDpathPCR extends Bundle()
val vec_nfregs = UFix(INPUT, 6) val vec_nfregs = UFix(INPUT, 6)
} }
class rocketDpathPCR extends Component class rocketDpathPCR(implicit conf: RocketConfiguration) extends Component
{ {
val io = new ioDpathPCR(); val io = new ioDpathPCR
val reg_epc = Reg() { UFix() }; val reg_epc = Reg() { UFix() };
val reg_badvaddr = Reg() { UFix() }; val reg_badvaddr = Reg() { UFix() };

22
rocket/src/main/scala/htif.scala
View File

@ -1,8 +1,8 @@
package rocket package rocket
import Chisel._ import Chisel._
import Node._; import Node._
import Constants._; import Constants._
import uncore._ import uncore._
class ioDebug extends Bundle class ioDebug extends Bundle
@ -23,21 +23,21 @@ class PCRReq extends Bundle
val data = Bits(width = 64) val data = Bits(width = 64)
} }
class ioHTIF extends Bundle class ioHTIF(implicit conf: RocketConfiguration) extends Bundle
{ {
val reset = Bool(INPUT) val reset = Bool(INPUT)
val debug = new ioDebug val debug = new ioDebug
val pcr_req = (new FIFOIO) { new PCRReq }.flip val pcr_req = (new FIFOIO) { new PCRReq }.flip
val pcr_rep = (new FIFOIO) { Bits(width = 64) } val pcr_rep = (new FIFOIO) { Bits(width = 64) }
val ipi_req = (new FIFOIO) { Bits(width = log2Up(NTILES)) } val ipi_req = (new FIFOIO) { Bits(width = log2Up(conf.ntiles)) }
val ipi_rep = (new FIFOIO) { Bool() }.flip val ipi_rep = (new FIFOIO) { Bool() }.flip
} }
class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends Component class rocketHTIF(w: Int)(implicit conf: RocketConfiguration) extends Component
{ {
val io = new Bundle { val io = new Bundle {
val host = new ioHost(w) val host = new ioHost(w)
val cpu = Vec(ncores) { new ioHTIF().flip } val cpu = Vec(conf.ntiles) { new ioHTIF().flip }
val mem = new ioTileLink val mem = new ioTileLink
} }
@ -78,7 +78,7 @@ class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends C
val cmd_readmem :: cmd_writemem :: cmd_readcr :: cmd_writecr :: cmd_ack :: cmd_nack :: Nil = Enum(6) { UFix() } val cmd_readmem :: cmd_writemem :: cmd_readcr :: cmd_writecr :: cmd_ack :: cmd_nack :: Nil = Enum(6) { UFix() }
val pcr_addr = addr(io.cpu(0).pcr_req.bits.addr.width-1, 0) val pcr_addr = addr(io.cpu(0).pcr_req.bits.addr.width-1, 0)
val pcr_coreid = if (ncores == 1) UFix(0) else addr(20+log2Up(ncores),20) val pcr_coreid = if (conf.ntiles == 1) UFix(0) else addr(20+log2Up(conf.ntiles),20)
val pcr_wdata = packet_ram(0) val pcr_wdata = packet_ram(0)
val bad_mem_packet = size(OFFSET_BITS-1-3,0).orR || addr(OFFSET_BITS-1-3,0).orR val bad_mem_packet = size(OFFSET_BITS-1-3,0).orR || addr(OFFSET_BITS-1-3,0).orR
@ -178,7 +178,7 @@ class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends C
} }
x_init.io.enq.valid := state === state_mem_req x_init.io.enq.valid := state === state_mem_req
val init_addr = addr.toUFix >> UFix(OFFSET_BITS-3) val init_addr = addr.toUFix >> UFix(OFFSET_BITS-3)
x_init.io.enq.bits := Mux(cmd === cmd_writemem, co.getUncachedWriteTransactionInit(init_addr, UFix(0)), co.getUncachedReadTransactionInit(init_addr, UFix(0))) x_init.io.enq.bits := Mux(cmd === cmd_writemem, conf.co.getUncachedWriteTransactionInit(init_addr, UFix(0)), conf.co.getUncachedReadTransactionInit(init_addr, UFix(0)))
io.mem.xact_init <> x_init.io.deq io.mem.xact_init <> x_init.io.deq
io.mem.xact_init_data.valid:= state === state_mem_wdata io.mem.xact_init_data.valid:= state === state_mem_wdata
io.mem.xact_init_data.bits.data := mem_req_data io.mem.xact_init_data.bits.data := mem_req_data
@ -189,8 +189,8 @@ class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends C
io.mem.probe_rep_data.valid := Bool(false) io.mem.probe_rep_data.valid := Bool(false)
io.mem.incoherent := Bool(true) io.mem.incoherent := Bool(true)
val pcrReadData = Vec(ncores) { Reg() { Bits(width = io.cpu(0).pcr_rep.bits.getWidth) } } val pcrReadData = Vec(conf.ntiles) { Reg() { Bits(width = io.cpu(0).pcr_rep.bits.getWidth) } }
for (i <- 0 until ncores) { for (i <- 0 until conf.ntiles) {
val my_reset = Reg(resetVal = Bool(true)) val my_reset = Reg(resetVal = Bool(true))
val my_ipi = Reg(resetVal = Bool(false)) val my_ipi = Reg(resetVal = Bool(false))
@ -207,7 +207,7 @@ class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends C
} }
cpu.ipi_rep.valid := my_ipi cpu.ipi_rep.valid := my_ipi
cpu.ipi_req.ready := Bool(true) cpu.ipi_req.ready := Bool(true)
for (j <- 0 until ncores) { for (j <- 0 until conf.ntiles) {
when (io.cpu(j).ipi_req.valid && io.cpu(j).ipi_req.bits === UFix(i)) { when (io.cpu(j).ipi_req.valid && io.cpu(j).ipi_req.bits === UFix(i)) {
my_ipi := Bool(true) my_ipi := Bool(true)
} }

15
rocket/src/main/scala/icache.scala
View File

@ -1,13 +1,12 @@
package rocket package rocket
import Chisel._; import Chisel._
import Node._; import Node._
import Constants._; import Constants._
import scala.math._;
import uncore._ import uncore._
import Util._ import Util._
case class ICacheConfig(co: CoherencePolicyWithUncached, sets: Int, assoc: Int, parity: Boolean = false) case class ICacheConfig(sets: Int, assoc: Int, parity: Boolean = false)
{ {
val w = 1 val w = 1
val ibytes = INST_BITS/8 val ibytes = INST_BITS/8
@ -51,7 +50,7 @@ class IOCPUFrontend extends Bundle {
val ptw = new IOTLBPTW().flip val ptw = new IOTLBPTW().flip
} }
class Frontend(c: ICacheConfig) extends Component class Frontend(c: ICacheConfig)(implicit conf: RocketConfiguration) extends Component
{ {
val io = new Bundle { val io = new Bundle {
val cpu = new IOCPUFrontend().flip val cpu = new IOCPUFrontend().flip
@ -123,7 +122,7 @@ class Frontend(c: ICacheConfig) extends Component
io.cpu.resp.bits.xcpt_if := s2_xcpt_if io.cpu.resp.bits.xcpt_if := s2_xcpt_if
} }
class ICache(c: ICacheConfig) extends Component class ICache(c: ICacheConfig)(implicit conf: RocketConfiguration) extends Component
{ {
val io = new Bundle { val io = new Bundle {
val req = new PipeIO()(new Bundle { val req = new PipeIO()(new Bundle {
@ -237,7 +236,7 @@ class ICache(c: ICacheConfig) extends Component
// output signals // output signals
io.resp.valid := s2_hit io.resp.valid := s2_hit
io.mem.xact_init.valid := (state === s_request) && finish_q.io.enq.ready io.mem.xact_init.valid := (state === s_request) && finish_q.io.enq.ready
io.mem.xact_init.bits := c.co.getUncachedReadTransactionInit(s2_addr >> UFix(c.offbits), UFix(0)) io.mem.xact_init.bits := conf.co.getUncachedReadTransactionInit(s2_addr >> UFix(c.offbits), UFix(0))
io.mem.xact_finish <> finish_q.io.deq io.mem.xact_finish <> finish_q.io.deq
// control state machine // control state machine

3
rocket/src/main/scala/instructions.scala
View File

@ -1,7 +1,8 @@
package rocket package rocket
import Chisel._ import Chisel._
import Node._; import Node._
import Constants._
object Instructions object Instructions
{ {

54
rocket/src/main/scala/nbdcache.scala
View File

@ -159,7 +159,7 @@ class MetaArrayReq extends Bundle {
val data = new MetaData() val data = new MetaData()
} }
class MSHR(id: Int, co: CoherencePolicy) extends Component { class MSHR(id: Int)(implicit conf: RocketConfiguration) extends Component {
val io = new Bundle { val io = new Bundle {
val req_pri_val = Bool(INPUT) val req_pri_val = Bool(INPUT)
val req_pri_rdy = Bool(OUTPUT) val req_pri_rdy = Bool(OUTPUT)
@ -197,7 +197,7 @@ class MSHR(id: Int, co: CoherencePolicy) extends Component {
val req_cmd = io.req_bits.cmd val req_cmd = io.req_bits.cmd
val req_use_rpq = (req_cmd != M_PFR) && (req_cmd != M_PFW) && (req_cmd != M_FLA) val req_use_rpq = (req_cmd != M_PFR) && (req_cmd != M_PFW) && (req_cmd != M_FLA)
val idx_match = req.idx === io.req_bits.idx val idx_match = req.idx === io.req_bits.idx
val sec_rdy = idx_match && !flush && (state === s_wb_req || state === s_wb_resp || state === s_meta_clear || (state === s_refill_req || state === s_refill_resp) && !co.needsTransactionOnSecondaryMiss(req_cmd, io.mem_req.bits)) val sec_rdy = idx_match && !flush && (state === s_wb_req || state === s_wb_resp || state === s_meta_clear || (state === s_refill_req || state === s_refill_resp) && !conf.co.needsTransactionOnSecondaryMiss(req_cmd, io.mem_req.bits))
val rpq = (new Queue(NRPQ)) { new RPQEntry } val rpq = (new Queue(NRPQ)) { new RPQEntry }
rpq.io.enq.valid := (io.req_pri_val && io.req_pri_rdy || io.req_sec_val && sec_rdy) && req_use_rpq rpq.io.enq.valid := (io.req_pri_val && io.req_pri_rdy || io.req_sec_val && sec_rdy) && req_use_rpq
@ -221,7 +221,7 @@ class MSHR(id: Int, co: CoherencePolicy) extends Component {
when (refill_done) { state := s_drain_rpq } when (refill_done) { state := s_drain_rpq }
when (reply) { when (reply) {
refill_count := refill_count + UFix(1) refill_count := refill_count + UFix(1)
line_state := co.newStateOnTransactionReply(io.mem_rep.bits, io.mem_req.bits) line_state := conf.co.newStateOnTransactionReply(io.mem_rep.bits, io.mem_req.bits)
} }
when (abort) { state := s_refill_req } when (abort) { state := s_refill_req }
} }
@ -243,13 +243,13 @@ class MSHR(id: Int, co: CoherencePolicy) extends Component {
} }
when (io.req_sec_val && io.req_sec_rdy) { // s_wb_req, s_wb_resp, s_refill_req when (io.req_sec_val && io.req_sec_rdy) { // s_wb_req, s_wb_resp, s_refill_req
xacx_type := co.getTransactionInitTypeOnSecondaryMiss(req_cmd, co.newStateOnFlush(), io.mem_req.bits) xacx_type := conf.co.getTransactionInitTypeOnSecondaryMiss(req_cmd, conf.co.newStateOnFlush(), io.mem_req.bits)
} }
when ((state === s_invalid) && io.req_pri_val) { when ((state === s_invalid) && io.req_pri_val) {
flush := req_cmd === M_FLA flush := req_cmd === M_FLA
line_state := co.newStateOnFlush() line_state := conf.co.newStateOnFlush()
refill_count := UFix(0) refill_count := UFix(0)
xacx_type := co.getTransactionInitTypeOnPrimaryMiss(req_cmd, co.newStateOnFlush()) xacx_type := conf.co.getTransactionInitTypeOnPrimaryMiss(req_cmd, conf.co.newStateOnFlush())
req := io.req_bits req := io.req_bits
when (io.req_bits.tag_miss) { when (io.req_bits.tag_miss) {
@ -268,7 +268,7 @@ class MSHR(id: Int, co: CoherencePolicy) extends Component {
io.meta_req.valid := (state === s_drain_rpq) && !rpq.io.deq.valid && !finish_q.io.deq.valid || (state === s_meta_clear) io.meta_req.valid := (state === s_drain_rpq) && !rpq.io.deq.valid && !finish_q.io.deq.valid || (state === s_meta_clear)
io.meta_req.bits.rw := Bool(true) io.meta_req.bits.rw := Bool(true)
io.meta_req.bits.idx := req.idx io.meta_req.bits.idx := req.idx
io.meta_req.bits.data.state := Mux(state === s_meta_clear, co.newStateOnFlush(), line_state) io.meta_req.bits.data.state := Mux(state === s_meta_clear, conf.co.newStateOnFlush(), line_state)
io.meta_req.bits.data.tag := req.tag io.meta_req.bits.data.tag := req.tag
io.meta_req.bits.way_en := req.way_oh io.meta_req.bits.way_en := req.way_oh
@ -293,7 +293,7 @@ class MSHR(id: Int, co: CoherencePolicy) extends Component {
io.replay.bits.way_oh := req.way_oh io.replay.bits.way_oh := req.way_oh
} }
class MSHRFile(co: CoherencePolicy) extends Component { class MSHRFile(implicit conf: RocketConfiguration) extends Component {
val io = new Bundle { val io = new Bundle {
val req = (new FIFOIO) { new MSHRReq }.flip val req = (new FIFOIO) { new MSHRReq }.flip
val secondary_miss = Bool(OUTPUT) val secondary_miss = Bool(OUTPUT)
@ -347,7 +347,7 @@ class MSHRFile(co: CoherencePolicy) extends Component {
var refill_probe_rdy = Bool(true) var refill_probe_rdy = Bool(true)
for (i <- 0 to NMSHR-1) { for (i <- 0 to NMSHR-1) {
val mshr = new MSHR(i, co) val mshr = new MSHR(i)
idxMatch(i) := mshr.io.idx_match idxMatch(i) := mshr.io.idx_match
tagList(i) := mshr.io.tag tagList(i) := mshr.io.tag
@ -416,7 +416,7 @@ class MSHRFile(co: CoherencePolicy) extends Component {
} }
class WritebackUnit(co: CoherencePolicy) extends Component { class WritebackUnit(implicit conf: RocketConfiguration) extends Component {
val io = new Bundle { val io = new Bundle {
val req = (new FIFOIO) { new WritebackReq() }.flip val req = (new FIFOIO) { new WritebackReq() }.flip
val probe = (new FIFOIO) { new WritebackReq() }.flip val probe = (new FIFOIO) { new WritebackReq() }.flip
@ -476,7 +476,7 @@ class WritebackUnit(co: CoherencePolicy) extends Component {
io.data_req.bits.data := Bits(0) io.data_req.bits.data := Bits(0)
io.mem_req.valid := valid && !cmd_sent io.mem_req.valid := valid && !cmd_sent
io.mem_req.bits.x_type := co.getTransactionInitTypeOnWriteback() io.mem_req.bits.x_type := conf.co.getTransactionInitTypeOnWriteback()
io.mem_req.bits.addr := Cat(req.tag, req.idx).toUFix io.mem_req.bits.addr := Cat(req.tag, req.idx).toUFix
io.mem_req.bits.tile_xact_id := req.tile_xact_id io.mem_req.bits.tile_xact_id := req.tile_xact_id
io.mem_req_data.valid := data_req_fired && !is_probe io.mem_req_data.valid := data_req_fired && !is_probe
@ -485,7 +485,7 @@ class WritebackUnit(co: CoherencePolicy) extends Component {
io.probe_rep_data.bits.data := io.data_resp io.probe_rep_data.bits.data := io.data_resp
} }
class ProbeUnit(co: CoherencePolicy) extends Component { class ProbeUnit(implicit conf: RocketConfiguration) extends Component {
val io = new Bundle { val io = new Bundle {
val req = (new FIFOIO) { new ProbeRequest }.flip val req = (new FIFOIO) { new ProbeRequest }.flip
val rep = (new FIFOIO) { new ProbeReply } val rep = (new FIFOIO) { new ProbeReply }
@ -511,7 +511,7 @@ class ProbeUnit(co: CoherencePolicy) extends Component {
state := s_writeback_resp state := s_writeback_resp
} }
when ((state === s_probe_rep) && io.meta_req.ready && io.rep.ready) { when ((state === s_probe_rep) && io.meta_req.ready && io.rep.ready) {
state := Mux(hit && co.needsWriteback(line_state), s_writeback_req, s_invalid) state := Mux(hit && conf.co.needsWriteback(line_state), s_writeback_req, s_invalid)
} }
when ((state === s_mshr_req) && io.mshr_req.ready) { when ((state === s_mshr_req) && io.mshr_req.ready) {
state := s_meta_req state := s_meta_req
@ -532,13 +532,13 @@ class ProbeUnit(co: CoherencePolicy) extends Component {
io.req.ready := state === s_invalid io.req.ready := state === s_invalid
io.rep.valid := state === s_probe_rep && io.meta_req.ready io.rep.valid := state === s_probe_rep && io.meta_req.ready
io.rep.bits := co.newProbeReply(req, Mux(hit, line_state, co.newStateOnFlush())) io.rep.bits := conf.co.newProbeReply(req, Mux(hit, line_state, conf.co.newStateOnFlush))
io.meta_req.valid := state === s_meta_req || state === s_meta_resp || state === s_mshr_req || state === s_probe_rep && hit io.meta_req.valid := state === s_meta_req || state === s_meta_resp || state === s_mshr_req || state === s_probe_rep && hit
io.meta_req.bits.way_en := Mux(state === s_probe_rep, way_oh, ~UFix(0, NWAYS)) io.meta_req.bits.way_en := Mux(state === s_probe_rep, way_oh, ~UFix(0, NWAYS))
io.meta_req.bits.rw := state === s_probe_rep io.meta_req.bits.rw := state === s_probe_rep
io.meta_req.bits.idx := req.addr io.meta_req.bits.idx := req.addr
io.meta_req.bits.data.state := co.newStateOnProbeRequest(req, line_state) io.meta_req.bits.data.state := conf.co.newStateOnProbeRequest(req, line_state)
io.meta_req.bits.data.tag := req.addr >> UFix(IDX_BITS) io.meta_req.bits.data.tag := req.addr >> UFix(IDX_BITS)
io.mshr_req.valid := state === s_meta_resp || state === s_mshr_req io.mshr_req.valid := state === s_meta_resp || state === s_mshr_req
io.addr := req.addr io.addr := req.addr
@ -549,7 +549,7 @@ class ProbeUnit(co: CoherencePolicy) extends Component {
io.wb_req.bits.tag := req.addr >> UFix(IDX_BITS) io.wb_req.bits.tag := req.addr >> UFix(IDX_BITS)
} }
class FlushUnit(lines: Int, co: CoherencePolicy) extends Component { class FlushUnit(lines: Int)(implicit conf: RocketConfiguration) extends Component {
val io = new Bundle { val io = new Bundle {
val req = (new FIFOIO) { Bool() }.flip val req = (new FIFOIO) { Bool() }.flip
val meta_req = (new FIFOIO) { new MetaArrayReq() } val meta_req = (new FIFOIO) { new MetaArrayReq() }
@ -594,7 +594,7 @@ class FlushUnit(lines: Int, co: CoherencePolicy) extends Component {
io.meta_req.bits.way_en := UFixToOH(way_cnt, NWAYS) io.meta_req.bits.way_en := UFixToOH(way_cnt, NWAYS)
io.meta_req.bits.idx := idx_cnt io.meta_req.bits.idx := idx_cnt
io.meta_req.bits.rw := (state === s_reset) io.meta_req.bits.rw := (state === s_reset)
io.meta_req.bits.data.state := co.newStateOnFlush() io.meta_req.bits.data.state := conf.co.newStateOnFlush()
io.meta_req.bits.data.tag := UFix(0) io.meta_req.bits.data.tag := UFix(0)
} }
@ -749,7 +749,7 @@ class ioHellaCache extends Bundle {
val xcpt = (new HellaCacheExceptions).asInput val xcpt = (new HellaCacheExceptions).asInput
} }
class HellaCache(co: CoherencePolicy) extends Component { class HellaCache(implicit conf: RocketConfiguration) extends Component {
val io = new Bundle { val io = new Bundle {
val cpu = (new ioHellaCache).flip val cpu = (new ioHellaCache).flip
val mem = new ioTileLink val mem = new ioTileLink
@ -802,10 +802,10 @@ class HellaCache(co: CoherencePolicy) extends Component {
val r_req_readwrite = r_req_read || r_req_write || r_req_prefetch val r_req_readwrite = r_req_read || r_req_write || r_req_prefetch
val nack_hit = Bool() val nack_hit = Bool()
val wb = new WritebackUnit(co) val wb = new WritebackUnit
val prober = new ProbeUnit(co) val prober = new ProbeUnit
val mshr = new MSHRFile(co) val mshr = new MSHRFile
val flusher = new FlushUnit(lines, co) val flusher = new FlushUnit(lines)
val replay_amo_val = mshr.io.data_req.valid && mshr.io.data_req.bits.cmd(3).toBool val replay_amo_val = mshr.io.data_req.valid && mshr.io.data_req.bits.cmd(3).toBool
// reset and flush unit // reset and flush unit
@ -864,10 +864,10 @@ class HellaCache(co: CoherencePolicy) extends Component {
val early_tag_nack = !meta_arb.io.in(3).ready val early_tag_nack = !meta_arb.io.in(3).ready
val cpu_req_ppn = Mux(prober.io.mshr_req.valid, prober.io.addr >> UFix(PGIDX_BITS-OFFSET_BITS), io.cpu.req.bits.ppn) val cpu_req_ppn = Mux(prober.io.mshr_req.valid, prober.io.addr >> UFix(PGIDX_BITS-OFFSET_BITS), io.cpu.req.bits.ppn)
val cpu_req_tag = Cat(cpu_req_ppn, r_cpu_req_idx)(tagmsb,taglsb) val cpu_req_tag = Cat(cpu_req_ppn, r_cpu_req_idx)(tagmsb,taglsb)
val tag_match_arr = (0 until NWAYS).map( w => co.isValid(meta.io.resp(w).state) && (meta.io.resp(w).tag === cpu_req_tag)) val tag_match_arr = (0 until NWAYS).map( w => conf.co.isValid(meta.io.resp(w).state) && (meta.io.resp(w).tag === cpu_req_tag))
val tag_match = Cat(Bits(0),tag_match_arr:_*).orR val tag_match = Cat(Bits(0),tag_match_arr:_*).orR
val tag_match_way_oh = Cat(Bits(0),tag_match_arr.reverse:_*)(NWAYS-1, 0) //TODO: use Vec val tag_match_way_oh = Cat(Bits(0),tag_match_arr.reverse:_*)(NWAYS-1, 0) //TODO: use Vec
val tag_hit_arr = (0 until NWAYS).map( w => co.isHit(r_cpu_req_cmd, meta.io.resp(w).state) && (meta.io.resp(w).tag === cpu_req_tag)) val tag_hit_arr = (0 until NWAYS).map( w => conf.co.isHit(r_cpu_req_cmd, meta.io.resp(w).state) && (meta.io.resp(w).tag === cpu_req_tag))
val tag_hit = Cat(Bits(0),tag_hit_arr:_*).orR val tag_hit = Cat(Bits(0),tag_hit_arr:_*).orR
val meta_resp_way_oh = Mux(meta.io.way_en === ~UFix(0, NWAYS), tag_match_way_oh, meta.io.way_en) val meta_resp_way_oh = Mux(meta.io.way_en === ~UFix(0, NWAYS), tag_match_way_oh, meta.io.way_en)
val data_resp_way_oh = Mux(data.io.way_en === ~UFix(0, NWAYS), tag_match_way_oh, data.io.way_en) val data_resp_way_oh = Mux(data.io.way_en === ~UFix(0, NWAYS), tag_match_way_oh, data.io.way_en)
@ -893,7 +893,7 @@ class HellaCache(co: CoherencePolicy) extends Component {
data_arb.io.in(0).bits.wmask := ~UFix(0, MEM_DATA_BITS/8) data_arb.io.in(0).bits.wmask := ~UFix(0, MEM_DATA_BITS/8)
data_arb.io.in(0).bits.data := io.mem.xact_rep.bits.data data_arb.io.in(0).bits.data := io.mem.xact_rep.bits.data
data_arb.io.in(0).bits.way_en := mshr.io.mem_resp_way_oh data_arb.io.in(0).bits.way_en := mshr.io.mem_resp_way_oh
data_arb.io.in(0).valid := io.mem.xact_rep.valid && co.messageUpdatesDataArray(io.mem.xact_rep.bits) data_arb.io.in(0).valid := io.mem.xact_rep.valid && conf.co.messageUpdatesDataArray(io.mem.xact_rep.bits)
// load hits // load hits
data_arb.io.in(4).bits.offset := io.cpu.req.bits.idx(offsetmsb,ramindexlsb) data_arb.io.in(4).bits.offset := io.cpu.req.bits.idx(offsetmsb,ramindexlsb)
@ -923,7 +923,7 @@ class HellaCache(co: CoherencePolicy) extends Component {
p_store_valid := p_store_valid && !drain_store || (r_cpu_req_val && tag_hit && r_req_store && mshr.io.req.ready && !nack_hit) || p_amo p_store_valid := p_store_valid && !drain_store || (r_cpu_req_val && tag_hit && r_req_store && mshr.io.req.ready && !nack_hit) || p_amo
// tag update after a store to an exclusive clean line. // tag update after a store to an exclusive clean line.
val new_hit_state = co.newStateOnHit(r_cpu_req_cmd, meta_resp_mux.state) val new_hit_state = conf.co.newStateOnHit(r_cpu_req_cmd, meta_resp_mux.state)
val set_hit_state = r_cpu_req_val && tag_hit && meta_resp_mux.state != new_hit_state val set_hit_state = r_cpu_req_val && tag_hit && meta_resp_mux.state != new_hit_state
meta.io.state_req.bits.rw := Bool(true) meta.io.state_req.bits.rw := Bool(true)
meta.io.state_req.bits.idx := Reg(r_cpu_req_idx(indexmsb,indexlsb)) meta.io.state_req.bits.idx := Reg(r_cpu_req_idx(indexmsb,indexlsb))
@ -947,7 +947,7 @@ class HellaCache(co: CoherencePolicy) extends Component {
// miss handling // miss handling
mshr.io.req.valid := r_cpu_req_val && r_req_readwrite && !nack_hit || flusher.io.mshr_req.valid mshr.io.req.valid := r_cpu_req_val && r_req_readwrite && !nack_hit || flusher.io.mshr_req.valid
mshr.io.req.bits.tag_miss := !tag_hit || flusher.io.mshr_req.valid mshr.io.req.bits.tag_miss := !tag_hit || flusher.io.mshr_req.valid
mshr.io.req.bits.old_dirty := co.needsWriteback(meta_wb_mux.state) && (!tag_match || flusher.io.mshr_req.valid) // don't wb upgrades mshr.io.req.bits.old_dirty := conf.co.needsWriteback(meta_wb_mux.state) && (!tag_match || flusher.io.mshr_req.valid) // don't wb upgrades
mshr.io.req.bits.old_tag := meta_wb_mux.tag mshr.io.req.bits.old_tag := meta_wb_mux.tag
mshr.io.req.bits.tag := cpu_req_tag mshr.io.req.bits.tag := cpu_req_tag
mshr.io.req.bits.idx := r_cpu_req_idx(indexmsb,indexlsb) mshr.io.req.bits.idx := r_cpu_req_idx(indexmsb,indexlsb)

28
rocket/src/main/scala/package.scala Normal file
View File

@ -0,0 +1,28 @@
package rocket
import rocket.constants._
import Chisel._
import scala.math._
//TODO: When compiler bug SI-5604 is fixed in 2.10, change object Constants to
// package object rocket and remove import Constants._'s from other files
object Constants extends
ScalarOpConstants with
uncore.constants.MemoryOpConstants with
PCRConstants with
InterruptConstants with
RocketDcacheConstants with
VectorOpConstants with
TLBConstants with
uncore.constants.MemoryInterfaceConstants
{
def HAVE_RVC = false
def HAVE_FPU = true
def HAVE_VEC = true
val MAX_THREADS =
hwacha.Constants.NUM_PVFB * hwacha.Constants.WIDTH_PVFB / hwacha.Constants.SZ_BANK
val START_ADDR = 0x2000
}

74
rocket/src/main/scala/ptw.scala
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@ -1,75 +1,9 @@
package rocket package rocket
import Chisel._; import Chisel._
import Node._; import Node._
import Constants._; import Constants._
import scala.math._; import scala.math._
class ioHellaCacheArbiter(n: Int) extends Bundle
{
val requestor = Vec(n) { new ioHellaCache() }.flip
val mem = new ioHellaCache
}
class rocketHellaCacheArbiter(n: Int) extends Component
{
val io = new ioHellaCacheArbiter(n)
require(DCACHE_TAG_BITS >= log2Up(n) + CPU_TAG_BITS)
var req_val = Bool(false)
var req_rdy = io.mem.req.ready
for (i <- 0 until n)
{
io.requestor(i).req.ready := req_rdy
req_val = req_val || io.requestor(i).req.valid
req_rdy = req_rdy && !io.requestor(i).req.valid
}
var req_cmd = io.requestor(n-1).req.bits.cmd
var req_type = io.requestor(n-1).req.bits.typ
var req_idx = io.requestor(n-1).req.bits.idx
var req_ppn = io.requestor(n-1).req.bits.ppn
var req_data = io.requestor(n-1).req.bits.data
var req_kill = io.requestor(n-1).req.bits.kill
var req_tag = io.requestor(n-1).req.bits.tag
for (i <- n-1 to 0 by -1)
{
val r = io.requestor(i).req
req_cmd = Mux(r.valid, r.bits.cmd, req_cmd)
req_type = Mux(r.valid, r.bits.typ, req_type)
req_idx = Mux(r.valid, r.bits.idx, req_idx)
req_ppn = Mux(Reg(r.valid), r.bits.ppn, req_ppn)
req_data = Mux(Reg(r.valid), r.bits.data, req_data)
req_kill = Mux(Reg(r.valid), r.bits.kill, req_kill)
req_tag = Mux(r.valid, Cat(r.bits.tag, UFix(i, log2Up(n))), req_tag)
}
io.mem.req.valid := req_val
io.mem.req.bits.cmd := req_cmd
io.mem.req.bits.typ := req_type
io.mem.req.bits.idx := req_idx
io.mem.req.bits.ppn := req_ppn
io.mem.req.bits.data := req_data
io.mem.req.bits.kill := req_kill
io.mem.req.bits.tag := req_tag
for (i <- 0 until n)
{
val r = io.requestor(i).resp
val x = io.requestor(i).xcpt
val tag_hit = io.mem.resp.bits.tag(log2Up(n)-1,0) === UFix(i)
x.ma.ld := io.mem.xcpt.ma.ld && Reg(io.requestor(i).req.valid)
x.ma.st := io.mem.xcpt.ma.st && Reg(io.requestor(i).req.valid)
r.valid := io.mem.resp.valid && tag_hit
r.bits.miss := io.mem.resp.bits.miss && tag_hit
r.bits.nack := io.mem.resp.bits.nack && Reg(io.requestor(i).req.valid)
r.bits.replay := io.mem.resp.bits.replay && tag_hit
r.bits.data := io.mem.resp.bits.data
r.bits.data_subword := io.mem.resp.bits.data_subword
r.bits.typ := io.mem.resp.bits.typ
r.bits.tag := io.mem.resp.bits.tag >> UFix(log2Up(n))
}
}
class ioPTW(n: Int) extends Bundle class ioPTW(n: Int) extends Bundle
{ {

3
rocket/src/main/scala/queues.scala
View File

@ -1,7 +1,8 @@
package rocket package rocket
import Chisel._ import Chisel._
import Node._; import Node._
import Constants._
class SkidBuffer[T <: Data](entries: Int, lateEnq: Boolean = false)(data: => T) extends Component class SkidBuffer[T <: Data](entries: Int, lateEnq: Boolean = false)(data: => T) extends Component
{ {

1
rocket/src/main/scala/rocket.config Normal file
View File

@ -0,0 +1 @@
NWAYS 4

17
rocket/src/main/scala/tile.scala
View File

@ -5,7 +5,7 @@ import Node._
import Constants._ import Constants._
import uncore._ import uncore._
class Tile(co: CoherencePolicyWithUncached, resetSignal: Bool = null) extends Component(resetSignal) class Tile(resetSignal: Bool = null)(implicit conf: RocketConfiguration) extends Component(resetSignal)
{ {
val io = new Bundle { val io = new Bundle {
val tilelink = new ioTileLink val tilelink = new ioTileLink
@ -13,12 +13,12 @@ class Tile(co: CoherencePolicyWithUncached, resetSignal: Bool = null) extends Co
} }
val cpu = new rocketProc val cpu = new rocketProc
val icache = new Frontend(ICacheConfig(co, 128, 4)) // 128 sets x 4 ways (32KB) val icache = new Frontend(ICacheConfig(128, 4)) // 128 sets x 4 ways (32KB)
val dcache = new HellaCache(co) val dcache = new HellaCache
val arbiter = new rocketMemArbiter(2 + (if (HAVE_VEC) 1 else 0)) val arbiter = new rocketMemArbiter(DMEM_PORTS)
arbiter.io.requestor(0) <> dcache.io.mem arbiter.io.requestor(DMEM_DCACHE) <> dcache.io.mem
arbiter.io.requestor(1) <> icache.io.mem arbiter.io.requestor(DMEM_ICACHE) <> icache.io.mem
io.tilelink.xact_init <> arbiter.io.mem.xact_init io.tilelink.xact_init <> arbiter.io.mem.xact_init
io.tilelink.xact_init_data <> dcache.io.mem.xact_init_data io.tilelink.xact_init_data <> dcache.io.mem.xact_init_data
@ -31,13 +31,12 @@ class Tile(co: CoherencePolicyWithUncached, resetSignal: Bool = null) extends Co
if (HAVE_VEC) if (HAVE_VEC)
{ {
val vicache = new Frontend(ICacheConfig(co, 128, 1)) // 128 sets x 1 ways (8KB) val vicache = new Frontend(ICacheConfig(128, 1)) // 128 sets x 1 ways (8KB)
arbiter.io.requestor(2) <> vicache.io.mem arbiter.io.requestor(DMEM_VICACHE) <> vicache.io.mem
cpu.io.vimem <> vicache.io.cpu cpu.io.vimem <> vicache.io.cpu
} }
cpu.io.host <> io.host cpu.io.host <> io.host
cpu.io.imem <> icache.io.cpu cpu.io.imem <> icache.io.cpu
cpu.io.dmem <> dcache.io.cpu cpu.io.dmem <> dcache.io.cpu
} }

33
rocket/src/main/scala/top.scala
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@ -1,19 +1,22 @@
package rocket package rocket
import Chisel._ import Chisel._
import Node._; import Node._
import Constants._
import uncore._ import uncore._
import Constants._;
import collection.mutable.ArrayBuffer import collection.mutable.ArrayBuffer
object DummyTopLevelConstants extends uncore.constants.CoherenceConfigConstants {
val NTILES = 1
val ENABLE_SHARING = true
val ENABLE_CLEAN_EXCLUSIVE = true
}
import DummyTopLevelConstants._
case class RocketConfiguration(ntiles: Int, co: CoherencePolicyWithUncached)
class Top extends Component class Top extends Component
{ {
val io = new Bundle {
val debug = new ioDebug
val host = new ioHost(HTIF_WIDTH)
val mem = new ioMemPipe
}
val co = if(ENABLE_SHARING) { val co = if(ENABLE_SHARING) {
if(ENABLE_CLEAN_EXCLUSIVE) new MESICoherence if(ENABLE_CLEAN_EXCLUSIVE) new MESICoherence
else new MSICoherence else new MSICoherence
@ -21,9 +24,17 @@ class Top extends Component
if(ENABLE_CLEAN_EXCLUSIVE) new MEICoherence if(ENABLE_CLEAN_EXCLUSIVE) new MEICoherence
else new MICoherence else new MICoherence
} }
implicit val rconf = RocketConfiguration(NTILES, co)
implicit val uconf = UncoreConfiguration(NTILES+1, log2Up(NTILES)+1)
val htif = new rocketHTIF(HTIF_WIDTH, NTILES, co) val io = new Bundle {
val hub = new CoherenceHubBroadcast(NTILES+1, co) val debug = new ioDebug
val host = new ioHost(HTIF_WIDTH)
val mem = new ioMemPipe
}
val htif = new rocketHTIF(HTIF_WIDTH)
val hub = new CoherenceHubBroadcast(co)
hub.io.tiles(NTILES) <> htif.io.mem hub.io.tiles(NTILES) <> htif.io.mem
io.host <> htif.io.host io.host <> htif.io.host
@ -36,7 +47,7 @@ class Top extends Component
for (i <- 0 until NTILES) { for (i <- 0 until NTILES) {
val hl = htif.io.cpu(i) val hl = htif.io.cpu(i)
val tl = hub.io.tiles(i) val tl = hub.io.tiles(i)
val tile = new Tile(co, resetSignal = hl.reset) val tile = new Tile(resetSignal = hl.reset)
tile.io.host.reset := Reg(Reg(hl.reset)) tile.io.host.reset := Reg(Reg(hl.reset))
tile.io.host.pcr_req <> Queue(hl.pcr_req) tile.io.host.pcr_req <> Queue(hl.pcr_req)

2
rocket/src/main/scala/util.scala
View File

@ -1,8 +1,6 @@
package rocket package rocket
import Chisel._ import Chisel._
import Node._
import scala.math._
object Util object Util
{ {