From b5ff43609275176480311c90b60d4ba7a3dfbcc2 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Fri, 5 Oct 2012 15:50:42 -0700 Subject: [PATCH 1/7] decode constant object split into multiple objects --- rocket/src/main/scala/ctrl.scala | 29 ++++++++++++++++++++--------- 1 file changed, 20 insertions(+), 9 deletions(-) diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala index 24304498..bf148c9a 100644 --- a/rocket/src/main/scala/ctrl.scala +++ b/rocket/src/main/scala/ctrl.scala @@ -90,7 +90,7 @@ class ioCtrlAll extends Bundle() val vec_iface = new ioCtrlVecInterface() } -object rocketCtrlDecode +abstract trait rocketCtrlDecodeConstants { val xpr64 = Y; @@ -102,7 +102,12 @@ object rocketCtrlDecode // | | | | | | | | | | | | | | | | | | | | | | | | | List(N, X,X,BR_X, X,X,A2_X, DW_X, FN_X, N,M_X, MT_X, X,MUL_X, X,DIV_X, X,WA_X, WB_X, PCR_X,SYNC_X,X,X,X,X) - val xdecode = Array( + val table: Array[(Bits, List[Bits])] +} + +object rocketCtrlXDecode extends rocketCtrlDecodeConstants +{ + val table = Array( // eret // fp_val renx2 | syscall // | vec_val | renx1 mem_val mul_val div_val wen pcr | | privileged @@ -209,8 +214,11 @@ object rocketCtrlDecode RDTIME-> List(Y, N,N,BR_N, N,N,A2_X, DW_XPR,FN_X, N,M_X, MT_X, N,MUL_X, N,DIV_X, Y,WA_RD,WB_TSC,PCR_N,SYNC_N,N,N,N,N), RDCYCLE-> List(Y, N,N,BR_N, N,N,A2_X, DW_XPR,FN_X, N,M_X, MT_X, N,MUL_X, N,DIV_X, Y,WA_RD,WB_TSC,PCR_N,SYNC_N,N,N,N,N), RDINSTRET-> List(Y, N,N,BR_N, N,N,A2_X, DW_XPR,FN_X, N,M_X, MT_X, N,MUL_X, N,DIV_X, Y,WA_RD,WB_IRT,PCR_N,SYNC_N,N,N,N,N)) - - val fdecode = Array( +} + +object rocketCtrlFDecode extends rocketCtrlDecodeConstants +{ + val table = Array( // eret // fp_val renx2 | syscall // | vec_val | renx1 mem_val mul_val div_val wen pcr | | privileged @@ -274,8 +282,11 @@ object rocketCtrlDecode FLD-> List(FPU_Y,Y,N,BR_N, N,Y,A2_ITYPE,DW_XPR,FN_ADD, Y,M_XRD, MT_D, N,MUL_X, N,DIV_X, N,WA_RD,WB_ALU,PCR_N,SYNC_N,N,N,N,N), FSW-> List(FPU_Y,Y,N,BR_N, N,Y,A2_BTYPE,DW_XPR,FN_ADD, Y,M_XWR, MT_W, N,MUL_X, N,DIV_X, N,WA_X, WB_ALU,PCR_N,SYNC_N,N,N,N,N), FSD-> List(FPU_Y,Y,N,BR_N, N,Y,A2_BTYPE,DW_XPR,FN_ADD, Y,M_XWR, MT_D, N,MUL_X, N,DIV_X, N,WA_X, WB_ALU,PCR_N,SYNC_N,N,N,N,N)) +} - val vdecode = Array( +object rocketCtrlVDecode extends rocketCtrlDecodeConstants +{ + val table = Array( // eret // fp_val renx2 | syscall // | vec_val | renx1 mem_val mul_val div_val wen pcr | | privileged @@ -334,11 +345,11 @@ class rocketCtrl extends Component { val io = new ioCtrlAll(); - var decode_table = rocketCtrlDecode.xdecode - if (HAVE_FPU) decode_table ++= rocketCtrlDecode.fdecode - if (HAVE_VEC) decode_table ++= rocketCtrlDecode.vdecode + var decode_table = rocketCtrlXDecode.table + if (HAVE_FPU) decode_table ++= rocketCtrlFDecode.table + if (HAVE_VEC) decode_table ++= rocketCtrlVDecode.table - val cs = DecodeLogic(io.dpath.inst, rocketCtrlDecode.decode_default, decode_table) + val cs = DecodeLogic(io.dpath.inst, rocketCtrlXDecode.decode_default, decode_table) val id_int_val :: id_fp_val :: id_vec_val :: id_br_type :: id_renx2 :: id_renx1 :: id_sel_alu2 :: id_fn_dw :: id_fn_alu :: cs0 = cs val id_mem_val :: id_mem_cmd :: id_mem_type :: id_mul_val :: id_mul_fn :: id_div_val :: id_div_fn :: id_wen :: id_sel_wa :: id_sel_wb :: cs1 = cs0 From dfdfddebe8ba743a858cb1c2468910e7c561ca44 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Sun, 7 Oct 2012 20:15:54 -0700 Subject: [PATCH 2/7] constants as traits --- rocket/src/main/scala/arbiter.scala | 5 +- rocket/src/main/scala/consts.scala | 78 +++++++++++++++--------- rocket/src/main/scala/ctrl.scala | 3 +- rocket/src/main/scala/ctrl_util.scala | 2 +- rocket/src/main/scala/dpath.scala | 3 +- rocket/src/main/scala/dpath_alu.scala | 3 +- rocket/src/main/scala/dpath_util.scala | 8 +-- rocket/src/main/scala/dtlb.scala | 8 +-- rocket/src/main/scala/htif.scala | 4 +- rocket/src/main/scala/icache.scala | 8 +-- rocket/src/main/scala/instructions.scala | 3 +- rocket/src/main/scala/itlb.scala | 8 +-- rocket/src/main/scala/memserdes.scala | 2 +- rocket/src/main/scala/package.scala | 29 +++++++++ rocket/src/main/scala/ptw.scala | 8 +-- rocket/src/main/scala/queues.scala | 3 +- rocket/src/main/scala/top.scala | 26 +++++--- rocket/src/main/scala/util.scala | 2 - 18 files changed, 128 insertions(+), 75 deletions(-) create mode 100644 rocket/src/main/scala/package.scala diff --git a/rocket/src/main/scala/arbiter.scala b/rocket/src/main/scala/arbiter.scala index 95432dc8..333397af 100644 --- a/rocket/src/main/scala/arbiter.scala +++ b/rocket/src/main/scala/arbiter.scala @@ -1,8 +1,7 @@ package rocket -import Chisel._; -import Node._; -import Constants._; +import Chisel._ +import Node._ import uncore._ class ioUncachedRequestor extends Bundle { diff --git a/rocket/src/main/scala/consts.scala b/rocket/src/main/scala/consts.scala index ac5de59d..1e3d0578 100644 --- a/rocket/src/main/scala/consts.scala +++ b/rocket/src/main/scala/consts.scala @@ -1,21 +1,40 @@ package rocket +package constants import Chisel._ import scala.math._ -object Constants -{ - val NTILES = 1 - val HAVE_RVC = false - val HAVE_FPU = true - val HAVE_VEC = true +abstract trait MulticoreConstants { + val NTILES: Int = 1 + val TILE_ID_BITS = log2Up(NTILES)+1 +} - val MAX_THREADS = - hwacha.Constants.NUM_PVFB * hwacha.Constants.WIDTH_PVFB / hwacha.Constants.SZ_BANK +abstract trait CoherenceConfigConstants { + val ENABLE_SHARING: Boolean + val ENABLE_CLEAN_EXCLUSIVE: Boolean +} +trait UncoreConstants { + val NGLOBAL_XACTS = 8 + val GLOBAL_XACT_ID_BITS = log2Up(NGLOBAL_XACTS) +} + +trait HTIFConstants { val HTIF_WIDTH = 16 val MEM_BACKUP_WIDTH = HTIF_WIDTH +} +abstract trait TileConfigConstants extends UncoreConstants with MulticoreConstants { + val HAVE_RVC: Boolean + val HAVE_FPU: Boolean + val HAVE_VEC: Boolean + def FPU_N = UFix(0, 1) + def FPU_Y = if (HAVE_FPU) UFix(1, 1) else FPU_N + def VEC_N = UFix(0, 1); + def VEC_Y = if (HAVE_VEC) UFix(1, 1) else VEC_N +} + +trait ScalarOpConstants { val BR_X = Bits("b????", 4) val BR_N = UFix(0, 4); val BR_EQ = UFix(1, 4); @@ -89,7 +108,9 @@ object Constants val DW_XPR = Y val RA = UFix(1, 5); +} +trait MemoryOpConstants { val MT_X = Bits("b???", 3); val MT_B = Bits("b000", 3); val MT_H = Bits("b001", 3); @@ -116,7 +137,9 @@ object Constants val M_XA_MAX = Bits("b1101", 4); val M_XA_MINU = Bits("b1110", 4); val M_XA_MAXU = Bits("b1111", 4); +} +trait PCRConstants { val PCR_X = Bits("b???", 3) val PCR_N = Bits(0,3) val PCR_F = Bits(1,3) // mfpcr @@ -161,11 +184,15 @@ object Constants val SR_VM = 8 // VM enable val SR_IM = 16 // interrupt mask val SR_IM_WIDTH = 8 +} +trait InterruptConstants { val CAUSE_INTERRUPT = 32 val IRQ_IPI = 5 val IRQ_TIMER = 7 - +} + +trait AddressConstants { val PADDR_BITS = 40; val VADDR_BITS = 43; val PGIDX_BITS = 13; @@ -173,8 +200,9 @@ object Constants val VPN_BITS = VADDR_BITS-PGIDX_BITS; val ASID_BITS = 7; val PERM_BITS = 6; +} - // rocketNBDCache parameters +abstract trait RocketDcacheConstants extends TileConfigConstants with AddressConstants { val DCACHE_PORTS = 3 val CPU_DATA_BITS = 64; val CPU_TAG_BITS = 9; @@ -188,17 +216,10 @@ object Constants val TAG_BITS = PADDR_BITS - OFFSET_BITS - IDX_BITS; val NWAYS = 4 require(IDX_BITS+OFFSET_BITS <= PGIDX_BITS); +} - // coherence parameters - val ENABLE_SHARING = true - val ENABLE_CLEAN_EXCLUSIVE = true - - val COHERENCE_DATA_BITS = (1 << OFFSET_BITS)*8 - val TILE_ID_BITS = log2Up(NTILES)+1 +trait TileLinkSizeConstants extends RocketDcacheConstants { val TILE_XACT_ID_BITS = log2Up(NMSHR)+3 - val NGLOBAL_XACTS = 8 - val GLOBAL_XACT_ID_BITS = log2Up(NGLOBAL_XACTS) - val X_INIT_TYPE_MAX_BITS = 2 val X_INIT_WRITE_MASK_BITS = OFFSET_BITS val X_INIT_SUBWORD_ADDR_BITS = log2Up(OFFSET_BITS) @@ -206,24 +227,21 @@ object Constants val X_REP_TYPE_MAX_BITS = 3 val P_REQ_TYPE_MAX_BITS = 2 val P_REP_TYPE_MAX_BITS = 3 +} - // external memory interface +trait MemoryInterfaceConstants extends UncoreConstants with TileLinkSizeConstants { val MEM_TAG_BITS = max(TILE_XACT_ID_BITS, GLOBAL_XACT_ID_BITS) val MEM_DATA_BITS = 128 val REFILL_CYCLES = (1 << OFFSET_BITS)*8/MEM_DATA_BITS - +} + +trait TLBConstants { val DTLB_ENTRIES = 16 val ITLB_ENTRIES = 8; val VITLB_ENTRIES = 4 - - val START_ADDR = 0x2000; - - val FPU_N = UFix(0, 1); - val FPU_Y = if (HAVE_FPU) UFix(1, 1) else FPU_N; - - val VEC_N = UFix(0, 1); - val VEC_Y = if (HAVE_VEC) UFix(1, 1) else VEC_N; +} +trait VectorOpConstants { val VEC_X = Bits("b??", 2).toUFix val VEC_FN_N = UFix(0, 2) val VEC_VL = UFix(1, 2) @@ -246,7 +264,9 @@ object Constants val VIMM2_RS2 = UFix(0, 1) val VIMM2_ALU = UFix(1, 1) val VIMM2_X = UFix(0, 1) +} +trait ArbiterConstants { val DTLB_CPU = 0 val DTLB_VEC = 1 val DTLB_VPF = 2 diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala index bf148c9a..3ea5105f 100644 --- a/rocket/src/main/scala/ctrl.scala +++ b/rocket/src/main/scala/ctrl.scala @@ -1,8 +1,7 @@ package rocket import Chisel._ -import Node._; - +import Node._ import Constants._ import Instructions._ import hwacha._ diff --git a/rocket/src/main/scala/ctrl_util.scala b/rocket/src/main/scala/ctrl_util.scala index 416033a6..34b6d40b 100644 --- a/rocket/src/main/scala/ctrl_util.scala +++ b/rocket/src/main/scala/ctrl_util.scala @@ -1,7 +1,7 @@ package rocket import Chisel._ -import Node._; +import Node._ class rocketCtrlSboard(entries: Int, nread: Int, nwrite: Int) extends Component { diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala index 84746631..a4d259c8 100644 --- a/rocket/src/main/scala/dpath.scala +++ b/rocket/src/main/scala/dpath.scala @@ -1,8 +1,7 @@ package rocket import Chisel._ -import Node._; - +import Node._ import Constants._ import Instructions._ import hwacha._ diff --git a/rocket/src/main/scala/dpath_alu.scala b/rocket/src/main/scala/dpath_alu.scala index 25fc2956..17404f56 100644 --- a/rocket/src/main/scala/dpath_alu.scala +++ b/rocket/src/main/scala/dpath_alu.scala @@ -1,8 +1,7 @@ package rocket import Chisel._ -import Node._; - +import Node._ import Constants._ import Instructions._ diff --git a/rocket/src/main/scala/dpath_util.scala b/rocket/src/main/scala/dpath_util.scala index f216e52a..e648a1e2 100644 --- a/rocket/src/main/scala/dpath_util.scala +++ b/rocket/src/main/scala/dpath_util.scala @@ -1,9 +1,9 @@ package rocket -import Chisel._; -import Node._; -import Constants._; -import scala.math._; +import Chisel._ +import Node._ +import Constants._ +import scala.math._ class ioDpathBTB extends Bundle() { diff --git a/rocket/src/main/scala/dtlb.scala b/rocket/src/main/scala/dtlb.scala index 6ce054dc..07c80159 100644 --- a/rocket/src/main/scala/dtlb.scala +++ b/rocket/src/main/scala/dtlb.scala @@ -1,10 +1,10 @@ package rocket -import Chisel._; -import Node._; -import Constants._; -import scala.math._; +import Chisel._ +import Node._ +import Constants._ import hwacha._ +import scala.math._ // ioDTLB_CPU also located in hwacha/src/vuVXU-Interface.scala // should keep them in sync diff --git a/rocket/src/main/scala/htif.scala b/rocket/src/main/scala/htif.scala index 335ef3cb..33a56c56 100644 --- a/rocket/src/main/scala/htif.scala +++ b/rocket/src/main/scala/htif.scala @@ -1,8 +1,8 @@ package rocket import Chisel._ -import Node._; -import Constants._; +import Node._ +import Constants._ import uncore._ class ioDebug extends Bundle diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala index 9b79e2ce..eb4c4b80 100644 --- a/rocket/src/main/scala/icache.scala +++ b/rocket/src/main/scala/icache.scala @@ -1,10 +1,10 @@ package rocket -import Chisel._; -import Node._; -import Constants._; -import scala.math._; +import Chisel._ +import Node._ +import Constants._ import uncore._ +import scala.math._ // interface between I$ and pipeline/ITLB (32 bits wide) class ioImem extends Bundle diff --git a/rocket/src/main/scala/instructions.scala b/rocket/src/main/scala/instructions.scala index 42aad6ef..377f2058 100644 --- a/rocket/src/main/scala/instructions.scala +++ b/rocket/src/main/scala/instructions.scala @@ -1,7 +1,8 @@ package rocket import Chisel._ -import Node._; +import Node._ +import Constants._ object Instructions { diff --git a/rocket/src/main/scala/itlb.scala b/rocket/src/main/scala/itlb.scala index dac04fa2..dda612a9 100644 --- a/rocket/src/main/scala/itlb.scala +++ b/rocket/src/main/scala/itlb.scala @@ -1,9 +1,9 @@ package rocket -import Chisel._; -import Node._; -import Constants._; -import scala.math._; +import Chisel._ +import Node._ +import Constants._ +import scala.math._ class ioCAM(entries: Int, addr_bits: Int, tag_bits: Int) extends Bundle { val clear = Bool(INPUT); diff --git a/rocket/src/main/scala/memserdes.scala b/rocket/src/main/scala/memserdes.scala index 712dec16..737b835b 100644 --- a/rocket/src/main/scala/memserdes.scala +++ b/rocket/src/main/scala/memserdes.scala @@ -3,8 +3,8 @@ package rocket import Chisel._ import Node._ import Constants._ -import scala.math._ import uncore._ +import scala.math._ class ioMemSerialized extends Bundle { diff --git a/rocket/src/main/scala/package.scala b/rocket/src/main/scala/package.scala new file mode 100644 index 00000000..108c5860 --- /dev/null +++ b/rocket/src/main/scala/package.scala @@ -0,0 +1,29 @@ +package rocket +import rocket.constants._ + +import Chisel._ +import scala.math._ + +//TODO: When compiler bug SI-5604 is fixed in 2.10, change object Constants to +// package object rocket and remove import Constants._'s from other files +object Constants extends HTIFConstants with + MemoryOpConstants with + PCRConstants with + InterruptConstants with + AddressConstants with + ArbiterConstants with + VectorOpConstants with + TLBConstants with + ScalarOpConstants with + MemoryInterfaceConstants +{ + val HAVE_RVC = false + val HAVE_FPU = true + val HAVE_VEC = true + + val MAX_THREADS = + hwacha.Constants.NUM_PVFB * hwacha.Constants.WIDTH_PVFB / hwacha.Constants.SZ_BANK + + val START_ADDR = 0x2000 + +} diff --git a/rocket/src/main/scala/ptw.scala b/rocket/src/main/scala/ptw.scala index d0c540c5..92550d77 100644 --- a/rocket/src/main/scala/ptw.scala +++ b/rocket/src/main/scala/ptw.scala @@ -1,9 +1,9 @@ package rocket -import Chisel._; -import Node._; -import Constants._; -import scala.math._; +import Chisel._ +import Node._ +import Constants._ +import scala.math._ class ioHellaCacheArbiter(n: Int) extends Bundle { diff --git a/rocket/src/main/scala/queues.scala b/rocket/src/main/scala/queues.scala index f414ff6e..7028c880 100644 --- a/rocket/src/main/scala/queues.scala +++ b/rocket/src/main/scala/queues.scala @@ -1,7 +1,8 @@ package rocket import Chisel._ -import Node._; +import Node._ +import Constants._ class SkidBuffer[T <: Data](resetSignal: Bool = null)(data: => T) extends Component(resetSignal) { diff --git a/rocket/src/main/scala/top.scala b/rocket/src/main/scala/top.scala index 4390f8d7..42413045 100644 --- a/rocket/src/main/scala/top.scala +++ b/rocket/src/main/scala/top.scala @@ -1,19 +1,21 @@ package rocket import Chisel._ -import Node._; +import Node._ +import Constants._ import uncore._ -import Constants._; import collection.mutable.ArrayBuffer -class Top extends Component -{ - val io = new Bundle { - val debug = new ioDebug - val host = new ioHost(HTIF_WIDTH) - val mem = new ioMemPipe - } +object DummyTopLevelConstants extends rocket.constants.CoherenceConfigConstants { +// val NTILES = 1 + val ENABLE_SHARING = true + val ENABLE_CLEAN_EXCLUSIVE = true +} +import DummyTopLevelConstants._ + +class Top extends Component +{ val co = if(ENABLE_SHARING) { if(ENABLE_CLEAN_EXCLUSIVE) new MESICoherence else new MSICoherence @@ -22,6 +24,12 @@ class Top extends Component else new MICoherence } + val io = new Bundle { + val debug = new ioDebug + val host = new ioHost(HTIF_WIDTH) + val mem = new ioMemPipe + } + val htif = new rocketHTIF(HTIF_WIDTH, NTILES, co) val hub = new CoherenceHubBroadcast(NTILES+1, co) hub.io.tiles(NTILES) <> htif.io.mem diff --git a/rocket/src/main/scala/util.scala b/rocket/src/main/scala/util.scala index 19856386..c60ae47d 100644 --- a/rocket/src/main/scala/util.scala +++ b/rocket/src/main/scala/util.scala @@ -1,8 +1,6 @@ package rocket import Chisel._ -import Node._ -import scala.math._ class Mux1H [T <: Data](n: Int)(gen: => T) extends Component { From 9025d0610c19168422287c993a2137bd6ef77eb3 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Sun, 7 Oct 2012 22:37:29 -0700 Subject: [PATCH 3/7] first pass at configuration object passed as implicit parameter --- rocket/src/main/scala/cpu.scala | 12 +++--- rocket/src/main/scala/dpath.scala | 6 +-- rocket/src/main/scala/dpath_util.scala | 4 +- rocket/src/main/scala/htif.scala | 18 ++++----- rocket/src/main/scala/icache.scala | 4 +- rocket/src/main/scala/nbdcache.scala | 54 +++++++++++++------------- rocket/src/main/scala/tile.scala | 8 ++-- rocket/src/main/scala/top.scala | 6 ++- 8 files changed, 57 insertions(+), 55 deletions(-) diff --git a/rocket/src/main/scala/cpu.scala b/rocket/src/main/scala/cpu.scala index c0a2f1c7..412d7e11 100644 --- a/rocket/src/main/scala/cpu.scala +++ b/rocket/src/main/scala/cpu.scala @@ -1,19 +1,19 @@ package rocket -import Chisel._; -import Node._; -import Constants._; +import Chisel._ +import Node._ +import Constants._ import hwacha._ -class ioRocket extends Bundle() +class ioRocket()(implicit conf: Configuration) extends Bundle { - val host = new ioHTIF + val host = new ioHTIF() val imem = (new ioImem).flip val vimem = (new ioImem).flip val dmem = new ioHellaCache } -class rocketProc extends Component +class rocketProc()(implicit conf: Configuration) extends Component { val io = new ioRocket diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala index a4d259c8..fc199520 100644 --- a/rocket/src/main/scala/dpath.scala +++ b/rocket/src/main/scala/dpath.scala @@ -12,9 +12,9 @@ class ioDpathImem extends Bundle() val resp_data = Bits(INPUT, 32); } -class ioDpathAll extends Bundle() +class ioDpathAll()(implicit conf: Configuration) extends Bundle() { - val host = new ioHTIF(); + val host = new ioHTIF() val ctrl = new ioCtrlDpath().flip val dmem = new ioHellaCache val dtlb = new ioDTLB_CPU_req_bundle().asOutput() @@ -28,7 +28,7 @@ class ioDpathAll extends Bundle() val vec_imul_resp = Bits(INPUT, hwacha.Constants.SZ_XLEN) } -class rocketDpath extends Component +class rocketDpath()(implicit conf: Configuration) extends Component { val io = new ioDpathAll(); diff --git a/rocket/src/main/scala/dpath_util.scala b/rocket/src/main/scala/dpath_util.scala index e648a1e2..66e6dec9 100644 --- a/rocket/src/main/scala/dpath_util.scala +++ b/rocket/src/main/scala/dpath_util.scala @@ -57,7 +57,7 @@ class rocketDpathBTB(entries: Int) extends Component io.target := mux.io.out.toUFix } -class ioDpathPCR extends Bundle() +class ioDpathPCR()(implicit conf: Configuration) extends Bundle() { val host = new ioHTIF() val r = new ioReadPort(); @@ -86,7 +86,7 @@ class ioDpathPCR extends Bundle() val vec_nfregs = UFix(INPUT, 6) } -class rocketDpathPCR extends Component +class rocketDpathPCR()(implicit conf: Configuration) extends Component { val io = new ioDpathPCR(); diff --git a/rocket/src/main/scala/htif.scala b/rocket/src/main/scala/htif.scala index 33a56c56..761bb59d 100644 --- a/rocket/src/main/scala/htif.scala +++ b/rocket/src/main/scala/htif.scala @@ -23,21 +23,21 @@ class PCRReq extends Bundle val data = Bits(width = 64) } -class ioHTIF extends Bundle +class ioHTIF()(implicit conf: Configuration) extends Bundle { val reset = Bool(INPUT) val debug = new ioDebug val pcr_req = (new FIFOIO) { new PCRReq }.flip val pcr_rep = (new FIFOIO) { Bits(width = 64) } - val ipi_req = (new FIFOIO) { Bits(width = log2Up(NTILES)) } + val ipi_req = (new FIFOIO) { Bits(width = log2Up(conf.ntiles)) } val ipi_rep = (new FIFOIO) { Bool() }.flip } -class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends Component +class rocketHTIF(w: Int)(implicit conf: Configuration) extends Component { val io = new Bundle { val host = new ioHost(w) - val cpu = Vec(ncores) { new ioHTIF().flip } + val cpu = Vec(conf.ntiles) { new ioHTIF().flip } val mem = new ioTileLink } @@ -78,7 +78,7 @@ class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends C val cmd_readmem :: cmd_writemem :: cmd_readcr :: cmd_writecr :: cmd_ack :: cmd_nack :: Nil = Enum(6) { UFix() } val pcr_addr = addr(io.cpu(0).pcr_req.bits.addr.width-1, 0) - val pcr_coreid = if (ncores == 1) UFix(0) else addr(20+log2Up(ncores),20) + val pcr_coreid = if (conf.ntiles == 1) UFix(0) else addr(20+log2Up(conf.ntiles),20) val pcr_wdata = packet_ram(0) val bad_mem_packet = size(OFFSET_BITS-1-3,0).orR || addr(OFFSET_BITS-1-3,0).orR @@ -178,7 +178,7 @@ class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends C } x_init.io.enq.valid := state === state_mem_req val init_addr = addr.toUFix >> UFix(OFFSET_BITS-3) - x_init.io.enq.bits := Mux(cmd === cmd_writemem, co.getUncachedWriteTransactionInit(init_addr, UFix(0)), co.getUncachedReadTransactionInit(init_addr, UFix(0))) + x_init.io.enq.bits := Mux(cmd === cmd_writemem, conf.co.getUncachedWriteTransactionInit(init_addr, UFix(0)), conf.co.getUncachedReadTransactionInit(init_addr, UFix(0))) io.mem.xact_init <> x_init.io.deq io.mem.xact_init_data.valid:= state === state_mem_wdata io.mem.xact_init_data.bits.data := mem_req_data @@ -189,8 +189,8 @@ class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends C io.mem.probe_rep_data.valid := Bool(false) io.mem.incoherent := Bool(true) - val pcr_mux = (new Mux1H(ncores)) { Bits(width = 64) } - for (i <- 0 until ncores) { + val pcr_mux = (new Mux1H(conf.ntiles)) { Bits(width = 64) } + for (i <- 0 until conf.ntiles) { val my_reset = Reg(resetVal = Bool(true)) val my_ipi = Reg(resetVal = Bool(false)) val rdata = Reg() { Bits() } @@ -208,7 +208,7 @@ class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends C } cpu.ipi_rep.valid := my_ipi cpu.ipi_req.ready := Bool(true) - for (j <- 0 until ncores) { + for (j <- 0 until conf.ntiles) { when (io.cpu(j).ipi_req.valid && io.cpu(j).ipi_req.bits === UFix(i)) { my_ipi := Bool(true) } diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala index eb4c4b80..c0fa675e 100644 --- a/rocket/src/main/scala/icache.scala +++ b/rocket/src/main/scala/icache.scala @@ -28,7 +28,7 @@ class ioRocketICache extends Bundle() // 32 bit wide cpu port, 128 bit wide memory port, 64 byte cachelines // parameters : // lines = # cache lines -class rocketICache(sets: Int, assoc: Int, co: CoherencePolicyWithUncached) extends Component +class rocketICache(sets: Int, assoc: Int)(implicit conf: Configuration) extends Component { val io = new ioRocketICache(); @@ -137,7 +137,7 @@ class rocketICache(sets: Int, assoc: Int, co: CoherencePolicyWithUncached) exten rdy := !io.cpu.itlb_miss && (state === s_ready) && (!r_cpu_req_val || tag_hit); io.cpu.resp_data := data_mux.io.out io.mem.xact_init.valid := (state === s_request) && finish_q.io.enq.ready - io.mem.xact_init.bits := co.getUncachedReadTransactionInit(r_cpu_miss_addr(tagmsb,indexlsb).toUFix, UFix(0)) + io.mem.xact_init.bits := conf.co.getUncachedReadTransactionInit(r_cpu_miss_addr(tagmsb,indexlsb).toUFix, UFix(0)) io.mem.xact_finish <> finish_q.io.deq // control state machine diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index 951d6adc..a2f0839a 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -159,7 +159,7 @@ class MetaArrayReq extends Bundle { val data = new MetaData() } -class MSHR(id: Int, co: CoherencePolicy) extends Component { +class MSHR(id: Int)(implicit conf: Configuration) extends Component { val io = new Bundle { val req_pri_val = Bool(INPUT) val req_pri_rdy = Bool(OUTPUT) @@ -197,7 +197,7 @@ class MSHR(id: Int, co: CoherencePolicy) extends Component { val req_cmd = io.req_bits.cmd val req_use_rpq = (req_cmd != M_PFR) && (req_cmd != M_PFW) && (req_cmd != M_FLA) val idx_match = req.idx === io.req_bits.idx - val sec_rdy = idx_match && !flush && (state === s_wb_req || state === s_wb_resp || state === s_meta_clear || (state === s_refill_req || state === s_refill_resp) && !co.needsTransactionOnSecondaryMiss(req_cmd, io.mem_req.bits)) + val sec_rdy = idx_match && !flush && (state === s_wb_req || state === s_wb_resp || state === s_meta_clear || (state === s_refill_req || state === s_refill_resp) && !conf.co.needsTransactionOnSecondaryMiss(req_cmd, io.mem_req.bits)) val rpq = (new Queue(NRPQ)) { new RPQEntry } rpq.io.enq.valid := (io.req_pri_val && io.req_pri_rdy || io.req_sec_val && sec_rdy) && req_use_rpq @@ -221,7 +221,7 @@ class MSHR(id: Int, co: CoherencePolicy) extends Component { when (refill_done) { state := s_drain_rpq } when (reply) { refill_count := refill_count + UFix(1) - line_state := co.newStateOnTransactionReply(io.mem_rep.bits, io.mem_req.bits) + line_state := conf.co.newStateOnTransactionReply(io.mem_rep.bits, io.mem_req.bits) } when (abort) { state := s_refill_req } } @@ -243,13 +243,13 @@ class MSHR(id: Int, co: CoherencePolicy) extends Component { } when (io.req_sec_val && io.req_sec_rdy) { // s_wb_req, s_wb_resp, s_refill_req - xacx_type := co.getTransactionInitTypeOnSecondaryMiss(req_cmd, co.newStateOnFlush(), io.mem_req.bits) + xacx_type := conf.co.getTransactionInitTypeOnSecondaryMiss(req_cmd, conf.co.newStateOnFlush(), io.mem_req.bits) } when ((state === s_invalid) && io.req_pri_val) { flush := req_cmd === M_FLA - line_state := co.newStateOnFlush() + line_state := conf.co.newStateOnFlush() refill_count := UFix(0) - xacx_type := co.getTransactionInitTypeOnPrimaryMiss(req_cmd, co.newStateOnFlush()) + xacx_type := conf.co.getTransactionInitTypeOnPrimaryMiss(req_cmd, conf.co.newStateOnFlush()) req := io.req_bits when (io.req_bits.tag_miss) { @@ -268,7 +268,7 @@ class MSHR(id: Int, co: CoherencePolicy) extends Component { io.meta_req.valid := (state === s_drain_rpq) && !rpq.io.deq.valid && !finish_q.io.deq.valid || (state === s_meta_clear) io.meta_req.bits.rw := Bool(true) io.meta_req.bits.idx := req.idx - io.meta_req.bits.data.state := Mux(state === s_meta_clear, co.newStateOnFlush(), line_state) + io.meta_req.bits.data.state := Mux(state === s_meta_clear, conf.co.newStateOnFlush(), line_state) io.meta_req.bits.data.tag := req.tag io.meta_req.bits.way_en := req.way_oh @@ -293,7 +293,7 @@ class MSHR(id: Int, co: CoherencePolicy) extends Component { io.replay.bits.way_oh := req.way_oh } -class MSHRFile(co: CoherencePolicy) extends Component { +class MSHRFile()(implicit conf: Configuration) extends Component { val io = new Bundle { val req = (new FIFOIO) { new MSHRReq }.flip val secondary_miss = Bool(OUTPUT) @@ -346,7 +346,7 @@ class MSHRFile(co: CoherencePolicy) extends Component { var refill_probe_rdy = Bool(true) for (i <- 0 to NMSHR-1) { - val mshr = new MSHR(i, co) + val mshr = new MSHR(i) tag_mux.io.sel(i) := mshr.io.idx_match tag_mux.io.in(i) := mshr.io.tag @@ -415,7 +415,7 @@ class MSHRFile(co: CoherencePolicy) extends Component { } -class WritebackUnit(co: CoherencePolicy) extends Component { +class WritebackUnit()(implicit conf: Configuration) extends Component { val io = new Bundle { val req = (new FIFOIO) { new WritebackReq() }.flip val probe = (new FIFOIO) { new WritebackReq() }.flip @@ -475,7 +475,7 @@ class WritebackUnit(co: CoherencePolicy) extends Component { io.data_req.bits.data := Bits(0) io.mem_req.valid := valid && !cmd_sent - io.mem_req.bits.x_type := co.getTransactionInitTypeOnWriteback() + io.mem_req.bits.x_type := conf.co.getTransactionInitTypeOnWriteback() io.mem_req.bits.addr := Cat(req.tag, req.idx).toUFix io.mem_req.bits.tile_xact_id := req.tile_xact_id io.mem_req_data.valid := data_req_fired && !is_probe @@ -484,7 +484,7 @@ class WritebackUnit(co: CoherencePolicy) extends Component { io.probe_rep_data.bits.data := io.data_resp } -class ProbeUnit(co: CoherencePolicy) extends Component { +class ProbeUnit()(implicit conf: Configuration) extends Component { val io = new Bundle { val req = (new FIFOIO) { new ProbeRequest }.flip val rep = (new FIFOIO) { new ProbeReply } @@ -510,7 +510,7 @@ class ProbeUnit(co: CoherencePolicy) extends Component { state := s_writeback_resp } when ((state === s_probe_rep) && io.meta_req.ready && io.rep.ready) { - state := Mux(hit && co.needsWriteback(line_state), s_writeback_req, s_invalid) + state := Mux(hit && conf.co.needsWriteback(line_state), s_writeback_req, s_invalid) } when ((state === s_mshr_req) && io.mshr_req.ready) { state := s_meta_req @@ -531,13 +531,13 @@ class ProbeUnit(co: CoherencePolicy) extends Component { io.req.ready := state === s_invalid io.rep.valid := state === s_probe_rep && io.meta_req.ready - io.rep.bits := co.newProbeReply(req, Mux(hit, line_state, co.newStateOnFlush())) + io.rep.bits := conf.co.newProbeReply(req, Mux(hit, line_state, conf.co.newStateOnFlush)) io.meta_req.valid := state === s_meta_req || state === s_meta_resp || state === s_mshr_req || state === s_probe_rep && hit io.meta_req.bits.way_en := Mux(state === s_probe_rep, way_oh, ~UFix(0, NWAYS)) io.meta_req.bits.rw := state === s_probe_rep io.meta_req.bits.idx := req.addr - io.meta_req.bits.data.state := co.newStateOnProbeRequest(req, line_state) + io.meta_req.bits.data.state := conf.co.newStateOnProbeRequest(req, line_state) io.meta_req.bits.data.tag := req.addr >> UFix(IDX_BITS) io.mshr_req.valid := state === s_meta_resp || state === s_mshr_req io.addr := req.addr @@ -548,7 +548,7 @@ class ProbeUnit(co: CoherencePolicy) extends Component { io.wb_req.bits.tag := req.addr >> UFix(IDX_BITS) } -class FlushUnit(lines: Int, co: CoherencePolicy) extends Component { +class FlushUnit(lines: Int)(implicit conf: Configuration) extends Component { val io = new Bundle { val req = (new FIFOIO) { Bool() }.flip val meta_req = (new FIFOIO) { new MetaArrayReq() } @@ -593,7 +593,7 @@ class FlushUnit(lines: Int, co: CoherencePolicy) extends Component { io.meta_req.bits.way_en := UFixToOH(way_cnt, NWAYS) io.meta_req.bits.idx := idx_cnt io.meta_req.bits.rw := (state === s_reset) - io.meta_req.bits.data.state := co.newStateOnFlush() + io.meta_req.bits.data.state := conf.co.newStateOnFlush() io.meta_req.bits.data.tag := UFix(0) } @@ -748,7 +748,7 @@ class ioHellaCache extends Bundle { val xcpt = (new HellaCacheExceptions).asInput } -class HellaCache(co: CoherencePolicy) extends Component { +class HellaCache()(implicit conf: Configuration) extends Component { val io = new Bundle { val cpu = (new ioHellaCache).flip val mem = new ioTileLink @@ -801,10 +801,10 @@ class HellaCache(co: CoherencePolicy) extends Component { val r_req_readwrite = r_req_read || r_req_write || r_req_prefetch val nack_hit = Bool() - val wb = new WritebackUnit(co) - val prober = new ProbeUnit(co) - val mshr = new MSHRFile(co) - val flusher = new FlushUnit(lines, co) + val wb = new WritebackUnit + val prober = new ProbeUnit + val mshr = new MSHRFile + val flusher = new FlushUnit(lines) val replay_amo_val = mshr.io.data_req.valid && mshr.io.data_req.bits.cmd(3).toBool // reset and flush unit @@ -863,10 +863,10 @@ class HellaCache(co: CoherencePolicy) extends Component { val early_tag_nack = !meta_arb.io.in(3).ready val cpu_req_ppn = Mux(prober.io.mshr_req.valid, prober.io.addr >> UFix(PGIDX_BITS-OFFSET_BITS), io.cpu.req.bits.ppn) val cpu_req_tag = Cat(cpu_req_ppn, r_cpu_req_idx)(tagmsb,taglsb) - val tag_match_arr = (0 until NWAYS).map( w => co.isValid(meta.io.resp(w).state) && (meta.io.resp(w).tag === cpu_req_tag)) + val tag_match_arr = (0 until NWAYS).map( w => conf.co.isValid(meta.io.resp(w).state) && (meta.io.resp(w).tag === cpu_req_tag)) val tag_match = Cat(Bits(0),tag_match_arr:_*).orR val tag_match_way_oh = Cat(Bits(0),tag_match_arr.reverse:_*)(NWAYS-1, 0) //TODO: use Vec - val tag_hit_arr = (0 until NWAYS).map( w => co.isHit(r_cpu_req_cmd, meta.io.resp(w).state) && (meta.io.resp(w).tag === cpu_req_tag)) + val tag_hit_arr = (0 until NWAYS).map( w => conf.co.isHit(r_cpu_req_cmd, meta.io.resp(w).state) && (meta.io.resp(w).tag === cpu_req_tag)) val tag_hit = Cat(Bits(0),tag_hit_arr:_*).orR val meta_resp_way_oh = Mux(meta.io.way_en === ~UFix(0, NWAYS), tag_match_way_oh, meta.io.way_en) val data_resp_way_oh = Mux(data.io.way_en === ~UFix(0, NWAYS), tag_match_way_oh, data.io.way_en) @@ -892,7 +892,7 @@ class HellaCache(co: CoherencePolicy) extends Component { data_arb.io.in(0).bits.wmask := ~UFix(0, MEM_DATA_BITS/8) data_arb.io.in(0).bits.data := io.mem.xact_rep.bits.data data_arb.io.in(0).bits.way_en := mshr.io.mem_resp_way_oh - data_arb.io.in(0).valid := io.mem.xact_rep.valid && co.messageUpdatesDataArray(io.mem.xact_rep.bits) + data_arb.io.in(0).valid := io.mem.xact_rep.valid && conf.co.messageUpdatesDataArray(io.mem.xact_rep.bits) // load hits data_arb.io.in(4).bits.offset := io.cpu.req.bits.idx(offsetmsb,ramindexlsb) @@ -922,7 +922,7 @@ class HellaCache(co: CoherencePolicy) extends Component { p_store_valid := p_store_valid && !drain_store || (r_cpu_req_val && tag_hit && r_req_store && mshr.io.req.ready && !nack_hit) || p_amo // tag update after a store to an exclusive clean line. - val new_hit_state = co.newStateOnHit(r_cpu_req_cmd, meta_resp_mux.state) + val new_hit_state = conf.co.newStateOnHit(r_cpu_req_cmd, meta_resp_mux.state) val set_hit_state = r_cpu_req_val && tag_hit && meta_resp_mux.state != new_hit_state meta.io.state_req.bits.rw := Bool(true) meta.io.state_req.bits.idx := Reg(r_cpu_req_idx(indexmsb,indexlsb)) @@ -946,7 +946,7 @@ class HellaCache(co: CoherencePolicy) extends Component { // miss handling mshr.io.req.valid := r_cpu_req_val && r_req_readwrite && !nack_hit || flusher.io.mshr_req.valid mshr.io.req.bits.tag_miss := !tag_hit || flusher.io.mshr_req.valid - mshr.io.req.bits.old_dirty := co.needsWriteback(meta_wb_mux.state) && (!tag_match || flusher.io.mshr_req.valid) // don't wb upgrades + mshr.io.req.bits.old_dirty := conf.co.needsWriteback(meta_wb_mux.state) && (!tag_match || flusher.io.mshr_req.valid) // don't wb upgrades mshr.io.req.bits.old_tag := meta_wb_mux.tag mshr.io.req.bits.tag := cpu_req_tag mshr.io.req.bits.idx := r_cpu_req_idx(indexmsb,indexlsb) diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala index 5e621808..30e961d6 100644 --- a/rocket/src/main/scala/tile.scala +++ b/rocket/src/main/scala/tile.scala @@ -5,7 +5,7 @@ import Node._ import Constants._ import uncore._ -class Tile(co: CoherencePolicyWithUncached, resetSignal: Bool = null) extends Component(resetSignal) +class Tile(resetSignal: Bool = null)(implicit conf: Configuration) extends Component(resetSignal) { val io = new Bundle { val tilelink = new ioTileLink @@ -13,8 +13,8 @@ class Tile(co: CoherencePolicyWithUncached, resetSignal: Bool = null) extends Co } val cpu = new rocketProc - val icache = new rocketICache(128, 4, co) // 128 sets x 4 ways (32KB) - val dcache = new HellaCache(co) + val icache = new rocketICache(128, 4) // 128 sets x 4 ways (32KB) + val dcache = new HellaCache val arbiter = new rocketMemArbiter(2 + (if (HAVE_VEC) 1 else 0)) arbiter.io.requestor(0) <> dcache.io.mem @@ -31,7 +31,7 @@ class Tile(co: CoherencePolicyWithUncached, resetSignal: Bool = null) extends Co if (HAVE_VEC) { - val vicache = new rocketICache(128, 1, co) // 128 sets x 1 ways (8KB) + val vicache = new rocketICache(128, 1) // 128 sets x 1 ways (8KB) arbiter.io.requestor(2) <> vicache.io.mem cpu.io.vimem <> vicache.io.cpu } diff --git a/rocket/src/main/scala/top.scala b/rocket/src/main/scala/top.scala index 42413045..35c41e79 100644 --- a/rocket/src/main/scala/top.scala +++ b/rocket/src/main/scala/top.scala @@ -13,6 +13,7 @@ object DummyTopLevelConstants extends rocket.constants.CoherenceConfigConstants } import DummyTopLevelConstants._ +case class Configuration(ntiles: Int, co: CoherencePolicyWithUncached) class Top extends Component { @@ -23,6 +24,7 @@ class Top extends Component if(ENABLE_CLEAN_EXCLUSIVE) new MEICoherence else new MICoherence } + implicit val conf = Configuration(NTILES, co) val io = new Bundle { val debug = new ioDebug @@ -30,7 +32,7 @@ class Top extends Component val mem = new ioMemPipe } - val htif = new rocketHTIF(HTIF_WIDTH, NTILES, co) + val htif = new rocketHTIF(HTIF_WIDTH) val hub = new CoherenceHubBroadcast(NTILES+1, co) hub.io.tiles(NTILES) <> htif.io.mem io.host <> htif.io.host @@ -44,7 +46,7 @@ class Top extends Component for (i <- 0 until NTILES) { val hl = htif.io.cpu(i) val tl = hub.io.tiles(i) - val tile = new Tile(co, resetSignal = hl.reset) + val tile = new Tile(resetSignal = hl.reset) tile.io.host.reset := Reg(Reg(hl.reset)) tile.io.host.pcr_req <> Queue(hl.pcr_req) From 5d2a470215ed1d5c23efa30055be5c1555fd2c7f Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Mon, 8 Oct 2012 13:06:45 -0700 Subject: [PATCH 4/7] all rocket-specific arbiters in one file and refactored traits slightly --- rocket/src/main/scala/arbiter.scala | 67 +++++++++++++++++++++ rocket/src/main/scala/consts.scala | 90 +++++++++++++++++------------ rocket/src/main/scala/cpu.scala | 62 ++++++++++---------- rocket/src/main/scala/package.scala | 11 ++-- rocket/src/main/scala/ptw.scala | 66 --------------------- rocket/src/main/scala/tile.scala | 8 +-- rocket/src/main/scala/top.scala | 4 +- 7 files changed, 162 insertions(+), 146 deletions(-) diff --git a/rocket/src/main/scala/arbiter.scala b/rocket/src/main/scala/arbiter.scala index 333397af..9e27f6ed 100644 --- a/rocket/src/main/scala/arbiter.scala +++ b/rocket/src/main/scala/arbiter.scala @@ -2,8 +2,75 @@ package rocket import Chisel._ import Node._ +import Constants._ import uncore._ +class ioHellaCacheArbiter(n: Int) extends Bundle +{ + val requestor = Vec(n) { new ioHellaCache() }.flip + val mem = new ioHellaCache +} + +class rocketHellaCacheArbiter(n: Int) extends Component +{ + val io = new ioHellaCacheArbiter(n) + require(DCACHE_TAG_BITS >= log2Up(n) + CPU_TAG_BITS) + + var req_val = Bool(false) + var req_rdy = io.mem.req.ready + for (i <- 0 until n) + { + io.requestor(i).req.ready := req_rdy + req_val = req_val || io.requestor(i).req.valid + req_rdy = req_rdy && !io.requestor(i).req.valid + } + + var req_cmd = io.requestor(n-1).req.bits.cmd + var req_type = io.requestor(n-1).req.bits.typ + var req_idx = io.requestor(n-1).req.bits.idx + var req_ppn = io.requestor(n-1).req.bits.ppn + var req_data = io.requestor(n-1).req.bits.data + var req_kill = io.requestor(n-1).req.bits.kill + var req_tag = io.requestor(n-1).req.bits.tag + for (i <- n-1 to 0 by -1) + { + val r = io.requestor(i).req + req_cmd = Mux(r.valid, r.bits.cmd, req_cmd) + req_type = Mux(r.valid, r.bits.typ, req_type) + req_idx = Mux(r.valid, r.bits.idx, req_idx) + req_ppn = Mux(Reg(r.valid), r.bits.ppn, req_ppn) + req_data = Mux(Reg(r.valid), r.bits.data, req_data) + req_kill = Mux(Reg(r.valid), r.bits.kill, req_kill) + req_tag = Mux(r.valid, Cat(r.bits.tag, UFix(i, log2Up(n))), req_tag) + } + + io.mem.req.valid := req_val + io.mem.req.bits.cmd := req_cmd + io.mem.req.bits.typ := req_type + io.mem.req.bits.idx := req_idx + io.mem.req.bits.ppn := req_ppn + io.mem.req.bits.data := req_data + io.mem.req.bits.kill := req_kill + io.mem.req.bits.tag := req_tag + + for (i <- 0 until n) + { + val r = io.requestor(i).resp + val x = io.requestor(i).xcpt + val tag_hit = io.mem.resp.bits.tag(log2Up(n)-1,0) === UFix(i) + x.ma.ld := io.mem.xcpt.ma.ld && Reg(io.requestor(i).req.valid) + x.ma.st := io.mem.xcpt.ma.st && Reg(io.requestor(i).req.valid) + r.valid := io.mem.resp.valid && tag_hit + r.bits.miss := io.mem.resp.bits.miss && tag_hit + r.bits.nack := io.mem.resp.bits.nack && Reg(io.requestor(i).req.valid) + r.bits.replay := io.mem.resp.bits.replay && tag_hit + r.bits.data := io.mem.resp.bits.data + r.bits.data_subword := io.mem.resp.bits.data_subword + r.bits.typ := io.mem.resp.bits.typ + r.bits.tag := io.mem.resp.bits.tag >> UFix(log2Up(n)) + } +} + class ioUncachedRequestor extends Bundle { val xact_init = (new FIFOIO) { new TransactionInit } val xact_abort = (new FIFOIO) { new TransactionAbort }.flip diff --git a/rocket/src/main/scala/consts.scala b/rocket/src/main/scala/consts.scala index 1e3d0578..9ec91845 100644 --- a/rocket/src/main/scala/consts.scala +++ b/rocket/src/main/scala/consts.scala @@ -5,7 +5,7 @@ import Chisel._ import scala.math._ abstract trait MulticoreConstants { - val NTILES: Int = 1 + val NTILES: Int val TILE_ID_BITS = log2Up(NTILES)+1 } @@ -19,19 +19,46 @@ trait UncoreConstants { val GLOBAL_XACT_ID_BITS = log2Up(NGLOBAL_XACTS) } -trait HTIFConstants { - val HTIF_WIDTH = 16 - val MEM_BACKUP_WIDTH = HTIF_WIDTH +trait TileLinkTypeConstants { + val X_INIT_TYPE_MAX_BITS = 2 + val X_REP_TYPE_MAX_BITS = 3 + val P_REQ_TYPE_MAX_BITS = 2 + val P_REP_TYPE_MAX_BITS = 3 } -abstract trait TileConfigConstants extends UncoreConstants with MulticoreConstants { - val HAVE_RVC: Boolean - val HAVE_FPU: Boolean - val HAVE_VEC: Boolean - def FPU_N = UFix(0, 1) - def FPU_Y = if (HAVE_FPU) UFix(1, 1) else FPU_N - def VEC_N = UFix(0, 1); - def VEC_Y = if (HAVE_VEC) UFix(1, 1) else VEC_N +trait TileLinkSizeConstants extends + RocketDcacheConstants with + TileLinkTypeConstants +{ + val TILE_XACT_ID_BITS = log2Up(NMSHR)+3 + val X_INIT_WRITE_MASK_BITS = OFFSET_BITS + val X_INIT_SUBWORD_ADDR_BITS = log2Up(OFFSET_BITS) + val X_INIT_ATOMIC_OP_BITS = 4 +} + +trait HTIFConstants { + val HTIF_WIDTH = 16 +} + +trait MemoryInterfaceConstants extends + HTIFConstants with + UncoreConstants with + TileLinkSizeConstants +{ + val MEM_TAG_BITS = max(TILE_XACT_ID_BITS, GLOBAL_XACT_ID_BITS) + val MEM_DATA_BITS = 128 + val REFILL_CYCLES = (1 << OFFSET_BITS)*8/MEM_DATA_BITS + val MEM_BACKUP_WIDTH = HTIF_WIDTH +} + +abstract trait TileConfigConstants { + def HAVE_RVC: Boolean + def HAVE_FPU: Boolean + def HAVE_VEC: Boolean + val FPU_N = UFix(0, 1) + val FPU_Y = if (HAVE_FPU) UFix(1, 1) else FPU_N + val VEC_N = UFix(0, 1); + val VEC_Y = if (HAVE_VEC) UFix(1, 1) else VEC_N } trait ScalarOpConstants { @@ -202,39 +229,21 @@ trait AddressConstants { val PERM_BITS = 6; } -abstract trait RocketDcacheConstants extends TileConfigConstants with AddressConstants { - val DCACHE_PORTS = 3 +abstract trait RocketDcacheConstants extends ArbiterConstants with AddressConstants { val CPU_DATA_BITS = 64; val CPU_TAG_BITS = 9; val DCACHE_TAG_BITS = log2Up(DCACHE_PORTS) + CPU_TAG_BITS - val OFFSET_BITS = 6; // log2(cache line size in bytes) + val LG_REFILL_WIDTH = 4; // log2(cache bus width in bytes) val NMSHR = if (HAVE_VEC) 4 else 2 // number of primary misses val NRPQ = 16; // number of secondary misses val NSDQ = 17; // number of secondary stores/AMOs - val LG_REFILL_WIDTH = 4; // log2(cache bus width in bytes) + val OFFSET_BITS = 6; // log2(cache line size in bytes) val IDX_BITS = 7; val TAG_BITS = PADDR_BITS - OFFSET_BITS - IDX_BITS; val NWAYS = 4 require(IDX_BITS+OFFSET_BITS <= PGIDX_BITS); } -trait TileLinkSizeConstants extends RocketDcacheConstants { - val TILE_XACT_ID_BITS = log2Up(NMSHR)+3 - val X_INIT_TYPE_MAX_BITS = 2 - val X_INIT_WRITE_MASK_BITS = OFFSET_BITS - val X_INIT_SUBWORD_ADDR_BITS = log2Up(OFFSET_BITS) - val X_INIT_ATOMIC_OP_BITS = 4 - val X_REP_TYPE_MAX_BITS = 3 - val P_REQ_TYPE_MAX_BITS = 2 - val P_REP_TYPE_MAX_BITS = 3 -} - -trait MemoryInterfaceConstants extends UncoreConstants with TileLinkSizeConstants { - val MEM_TAG_BITS = max(TILE_XACT_ID_BITS, GLOBAL_XACT_ID_BITS) - val MEM_DATA_BITS = 128 - val REFILL_CYCLES = (1 << OFFSET_BITS)*8/MEM_DATA_BITS -} - trait TLBConstants { val DTLB_ENTRIES = 16 val ITLB_ENTRIES = 8; @@ -266,12 +275,19 @@ trait VectorOpConstants { val VIMM2_X = UFix(0, 1) } -trait ArbiterConstants { +abstract trait ArbiterConstants extends TileConfigConstants { + val DTLB_PORTS = 3 val DTLB_CPU = 0 val DTLB_VEC = 1 val DTLB_VPF = 2 - val DMEM_CPU = 0 - val DMEM_PTW = 1 - val DMEM_VU = 2 + val DCACHE_PORTS = 3 + val DCACHE_CPU = 0 + val DCACHE_PTW = 1 + val DCACHE_VU = 2 + + val DMEM_PORTS = if (HAVE_VEC) 3 else 2 + val DMEM_DCACHE = 0 + val DMEM_ICACHE = 1 + val DMEM_VICACHE = 2 } diff --git a/rocket/src/main/scala/cpu.scala b/rocket/src/main/scala/cpu.scala index 412d7e11..8f7f49fc 100644 --- a/rocket/src/main/scala/cpu.scala +++ b/rocket/src/main/scala/cpu.scala @@ -30,8 +30,8 @@ class rocketProc()(implicit conf: Configuration) extends Component { vu = new vu() // cpu, vector prefetch, and vector use the DTLB - val dtlbarb = new RRArbiter(3)({new ioDTLB_CPU_req_bundle()}) - val dtlbchosen = Reg(resetVal=Bits(DTLB_CPU,log2Up(3))) + val dtlbarb = new RRArbiter(DTLB_PORTS)({new ioDTLB_CPU_req_bundle()}) + val dtlbchosen = Reg(resetVal=Bits(DTLB_CPU,log2Up(DTLB_PORTS))) when( dtlb.io.cpu_req.ready && dtlbarb.io.out.valid ) { dtlbchosen := dtlbarb.io.chosen } // tlb respones come out a cycle later @@ -86,15 +86,15 @@ class rocketProc()(implicit conf: Configuration) extends Component dtlb.io.invalidate := dpath.io.ptbr_wen dtlb.io.status := dpath.io.ctrl.status - arb.io.requestor(DMEM_CPU).req.bits.ppn := dtlb.io.cpu_resp.ppn - ctrl.io.dmem.req.ready := dtlb.io.cpu_req.ready && arb.io.requestor(DMEM_CPU).req.ready + arb.io.requestor(DCACHE_CPU).req.bits.ppn := dtlb.io.cpu_resp.ppn + ctrl.io.dmem.req.ready := dtlb.io.cpu_req.ready && arb.io.requestor(DCACHE_CPU).req.ready // connect page table walker to TLBs, page table base register (from PCR) // and D$ arbiter (selects between requests from pipeline and PTW, PTW has priority) ptw.io.requestor(0) <> itlb.io.ptw ptw.io.requestor(1) <> dtlb.io.ptw ptw.io.ptbr := dpath.io.ptbr; - arb.io.requestor(DMEM_PTW) <> ptw.io.mem + arb.io.requestor(DCACHE_PTW) <> ptw.io.mem arb.io.mem <> io.dmem ctrl.io.dpath <> dpath.io.ctrl; @@ -119,17 +119,17 @@ class rocketProc()(implicit conf: Configuration) extends Component // connect arbiter to ctrl+dpath+DTLB //TODO: views on nested bundles? - arb.io.requestor(DMEM_CPU).resp <> ctrl.io.dmem.resp - arb.io.requestor(DMEM_CPU).xcpt <> ctrl.io.dmem.xcpt - arb.io.requestor(DMEM_CPU).resp <> dpath.io.dmem.resp - arb.io.requestor(DMEM_CPU).req.valid := ctrl.io.dmem.req.valid - ctrl.io.dmem.req.ready := arb.io.requestor(DMEM_CPU).req.ready - arb.io.requestor(DMEM_CPU).req.bits.kill := ctrl.io.dmem.req.bits.kill - arb.io.requestor(DMEM_CPU).req.bits.cmd := ctrl.io.dmem.req.bits.cmd - arb.io.requestor(DMEM_CPU).req.bits.typ := ctrl.io.dmem.req.bits.typ - arb.io.requestor(DMEM_CPU).req.bits.idx := dpath.io.dmem.req.bits.idx - arb.io.requestor(DMEM_CPU).req.bits.tag := dpath.io.dmem.req.bits.tag - arb.io.requestor(DMEM_CPU).req.bits.data := dpath.io.dmem.req.bits.data + arb.io.requestor(DCACHE_CPU).resp <> ctrl.io.dmem.resp + arb.io.requestor(DCACHE_CPU).xcpt <> ctrl.io.dmem.xcpt + arb.io.requestor(DCACHE_CPU).resp <> dpath.io.dmem.resp + arb.io.requestor(DCACHE_CPU).req.valid := ctrl.io.dmem.req.valid + ctrl.io.dmem.req.ready := arb.io.requestor(DCACHE_CPU).req.ready + arb.io.requestor(DCACHE_CPU).req.bits.kill := ctrl.io.dmem.req.bits.kill + arb.io.requestor(DCACHE_CPU).req.bits.cmd := ctrl.io.dmem.req.bits.cmd + arb.io.requestor(DCACHE_CPU).req.bits.typ := ctrl.io.dmem.req.bits.typ + arb.io.requestor(DCACHE_CPU).req.bits.idx := dpath.io.dmem.req.bits.idx + arb.io.requestor(DCACHE_CPU).req.bits.tag := dpath.io.dmem.req.bits.tag + arb.io.requestor(DCACHE_CPU).req.bits.data := dpath.io.dmem.req.bits.data var fpu: rocketFPU = null if (HAVE_FPU) @@ -217,21 +217,21 @@ class rocketProc()(implicit conf: Configuration) extends Component storegen.io.typ := vu.io.dmem_req.bits.typ storegen.io.din := vu.io.dmem_req.bits.data - arb.io.requestor(DMEM_VU).req.valid := vu.io.dmem_req.valid - arb.io.requestor(DMEM_VU).req.bits.kill := vu.io.dmem_req.bits.kill - arb.io.requestor(DMEM_VU).req.bits.cmd := vu.io.dmem_req.bits.cmd - arb.io.requestor(DMEM_VU).req.bits.typ := vu.io.dmem_req.bits.typ - arb.io.requestor(DMEM_VU).req.bits.idx := vu.io.dmem_req.bits.idx - arb.io.requestor(DMEM_VU).req.bits.ppn := Reg(vu.io.dmem_req.bits.ppn) - arb.io.requestor(DMEM_VU).req.bits.data := Reg(storegen.io.dout) - arb.io.requestor(DMEM_VU).req.bits.tag := vu.io.dmem_req.bits.tag + arb.io.requestor(DCACHE_VU).req.valid := vu.io.dmem_req.valid + arb.io.requestor(DCACHE_VU).req.bits.kill := vu.io.dmem_req.bits.kill + arb.io.requestor(DCACHE_VU).req.bits.cmd := vu.io.dmem_req.bits.cmd + arb.io.requestor(DCACHE_VU).req.bits.typ := vu.io.dmem_req.bits.typ + arb.io.requestor(DCACHE_VU).req.bits.idx := vu.io.dmem_req.bits.idx + arb.io.requestor(DCACHE_VU).req.bits.ppn := Reg(vu.io.dmem_req.bits.ppn) + arb.io.requestor(DCACHE_VU).req.bits.data := Reg(storegen.io.dout) + arb.io.requestor(DCACHE_VU).req.bits.tag := vu.io.dmem_req.bits.tag - vu.io.dmem_req.ready := arb.io.requestor(DMEM_VU).req.ready - vu.io.dmem_resp.valid := Reg(arb.io.requestor(DMEM_VU).resp.valid) - vu.io.dmem_resp.bits.nack := arb.io.requestor(DMEM_VU).resp.bits.nack - vu.io.dmem_resp.bits.data := arb.io.requestor(DMEM_VU).resp.bits.data_subword - vu.io.dmem_resp.bits.tag := Reg(arb.io.requestor(DMEM_VU).resp.bits.tag) - vu.io.dmem_resp.bits.typ := Reg(arb.io.requestor(DMEM_VU).resp.bits.typ) + vu.io.dmem_req.ready := arb.io.requestor(DCACHE_VU).req.ready + vu.io.dmem_resp.valid := Reg(arb.io.requestor(DCACHE_VU).resp.valid) + vu.io.dmem_resp.bits.nack := arb.io.requestor(DCACHE_VU).resp.bits.nack + vu.io.dmem_resp.bits.data := arb.io.requestor(DCACHE_VU).resp.bits.data_subword + vu.io.dmem_resp.bits.tag := Reg(arb.io.requestor(DCACHE_VU).resp.bits.tag) + vu.io.dmem_resp.bits.typ := Reg(arb.io.requestor(DCACHE_VU).resp.bits.typ) // share vector integer multiplier with rocket dpath.io.vec_imul_req <> vu.io.cp_imul_req @@ -243,7 +243,7 @@ class rocketProc()(implicit conf: Configuration) extends Component } else { - arb.io.requestor(DMEM_VU).req.valid := Bool(false) + arb.io.requestor(DCACHE_VU).req.valid := Bool(false) if (HAVE_FPU) { fpu.io.sfma.valid := Bool(false) diff --git a/rocket/src/main/scala/package.scala b/rocket/src/main/scala/package.scala index 108c5860..aaa06dcd 100644 --- a/rocket/src/main/scala/package.scala +++ b/rocket/src/main/scala/package.scala @@ -6,20 +6,19 @@ import scala.math._ //TODO: When compiler bug SI-5604 is fixed in 2.10, change object Constants to // package object rocket and remove import Constants._'s from other files -object Constants extends HTIFConstants with +object Constants extends + ScalarOpConstants with MemoryOpConstants with PCRConstants with InterruptConstants with AddressConstants with - ArbiterConstants with VectorOpConstants with TLBConstants with - ScalarOpConstants with MemoryInterfaceConstants { - val HAVE_RVC = false - val HAVE_FPU = true - val HAVE_VEC = true + def HAVE_RVC = false + def HAVE_FPU = true + def HAVE_VEC = true val MAX_THREADS = hwacha.Constants.NUM_PVFB * hwacha.Constants.WIDTH_PVFB / hwacha.Constants.SZ_BANK diff --git a/rocket/src/main/scala/ptw.scala b/rocket/src/main/scala/ptw.scala index 92550d77..11d8f0b8 100644 --- a/rocket/src/main/scala/ptw.scala +++ b/rocket/src/main/scala/ptw.scala @@ -5,72 +5,6 @@ import Node._ import Constants._ import scala.math._ -class ioHellaCacheArbiter(n: Int) extends Bundle -{ - val requestor = Vec(n) { new ioHellaCache() }.flip - val mem = new ioHellaCache -} - -class rocketHellaCacheArbiter(n: Int) extends Component -{ - val io = new ioHellaCacheArbiter(n) - require(DCACHE_TAG_BITS >= log2Up(n) + CPU_TAG_BITS) - - var req_val = Bool(false) - var req_rdy = io.mem.req.ready - for (i <- 0 until n) - { - io.requestor(i).req.ready := req_rdy - req_val = req_val || io.requestor(i).req.valid - req_rdy = req_rdy && !io.requestor(i).req.valid - } - - var req_cmd = io.requestor(n-1).req.bits.cmd - var req_type = io.requestor(n-1).req.bits.typ - var req_idx = io.requestor(n-1).req.bits.idx - var req_ppn = io.requestor(n-1).req.bits.ppn - var req_data = io.requestor(n-1).req.bits.data - var req_kill = io.requestor(n-1).req.bits.kill - var req_tag = io.requestor(n-1).req.bits.tag - for (i <- n-1 to 0 by -1) - { - val r = io.requestor(i).req - req_cmd = Mux(r.valid, r.bits.cmd, req_cmd) - req_type = Mux(r.valid, r.bits.typ, req_type) - req_idx = Mux(r.valid, r.bits.idx, req_idx) - req_ppn = Mux(Reg(r.valid), r.bits.ppn, req_ppn) - req_data = Mux(Reg(r.valid), r.bits.data, req_data) - req_kill = Mux(Reg(r.valid), r.bits.kill, req_kill) - req_tag = Mux(r.valid, Cat(r.bits.tag, UFix(i, log2Up(n))), req_tag) - } - - io.mem.req.valid := req_val - io.mem.req.bits.cmd := req_cmd - io.mem.req.bits.typ := req_type - io.mem.req.bits.idx := req_idx - io.mem.req.bits.ppn := req_ppn - io.mem.req.bits.data := req_data - io.mem.req.bits.kill := req_kill - io.mem.req.bits.tag := req_tag - - for (i <- 0 until n) - { - val r = io.requestor(i).resp - val x = io.requestor(i).xcpt - val tag_hit = io.mem.resp.bits.tag(log2Up(n)-1,0) === UFix(i) - x.ma.ld := io.mem.xcpt.ma.ld && Reg(io.requestor(i).req.valid) - x.ma.st := io.mem.xcpt.ma.st && Reg(io.requestor(i).req.valid) - r.valid := io.mem.resp.valid && tag_hit - r.bits.miss := io.mem.resp.bits.miss && tag_hit - r.bits.nack := io.mem.resp.bits.nack && Reg(io.requestor(i).req.valid) - r.bits.replay := io.mem.resp.bits.replay && tag_hit - r.bits.data := io.mem.resp.bits.data - r.bits.data_subword := io.mem.resp.bits.data_subword - r.bits.typ := io.mem.resp.bits.typ - r.bits.tag := io.mem.resp.bits.tag >> UFix(log2Up(n)) - } -} - class ioPTW(n: Int) extends Bundle { val requestor = Vec(n) { new ioTLB_PTW }.flip diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala index 30e961d6..69aef22d 100644 --- a/rocket/src/main/scala/tile.scala +++ b/rocket/src/main/scala/tile.scala @@ -16,9 +16,9 @@ class Tile(resetSignal: Bool = null)(implicit conf: Configuration) extends Compo val icache = new rocketICache(128, 4) // 128 sets x 4 ways (32KB) val dcache = new HellaCache - val arbiter = new rocketMemArbiter(2 + (if (HAVE_VEC) 1 else 0)) - arbiter.io.requestor(0) <> dcache.io.mem - arbiter.io.requestor(1) <> icache.io.mem + val arbiter = new rocketMemArbiter(DMEM_PORTS) + arbiter.io.requestor(DMEM_DCACHE) <> dcache.io.mem + arbiter.io.requestor(DMEM_ICACHE) <> icache.io.mem io.tilelink.xact_init <> arbiter.io.mem.xact_init io.tilelink.xact_init_data <> dcache.io.mem.xact_init_data @@ -32,7 +32,7 @@ class Tile(resetSignal: Bool = null)(implicit conf: Configuration) extends Compo if (HAVE_VEC) { val vicache = new rocketICache(128, 1) // 128 sets x 1 ways (8KB) - arbiter.io.requestor(2) <> vicache.io.mem + arbiter.io.requestor(DMEM_VICACHE) <> vicache.io.mem cpu.io.vimem <> vicache.io.cpu } diff --git a/rocket/src/main/scala/top.scala b/rocket/src/main/scala/top.scala index 35c41e79..7b29021c 100644 --- a/rocket/src/main/scala/top.scala +++ b/rocket/src/main/scala/top.scala @@ -6,8 +6,8 @@ import Constants._ import uncore._ import collection.mutable.ArrayBuffer -object DummyTopLevelConstants extends rocket.constants.CoherenceConfigConstants { -// val NTILES = 1 +object DummyTopLevelConstants extends rocket.constants.CoherenceConfigConstants with rocket.constants.MulticoreConstants { + val NTILES = 1 val ENABLE_SHARING = true val ENABLE_CLEAN_EXCLUSIVE = true } From a7a4e6569040683e2b0d9703bb13953ed91280b3 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Mon, 15 Oct 2012 16:04:25 -0700 Subject: [PATCH 5/7] Initial verison of reading config from files --- rocket/src/main/scala/config.scala | 56 +++++++++++++++++++++++++++++ rocket/src/main/scala/rocket.config | 1 + 2 files changed, 57 insertions(+) create mode 100644 rocket/src/main/scala/config.scala create mode 100644 rocket/src/main/scala/rocket.config diff --git a/rocket/src/main/scala/config.scala b/rocket/src/main/scala/config.scala new file mode 100644 index 00000000..13d7344a --- /dev/null +++ b/rocket/src/main/scala/config.scala @@ -0,0 +1,56 @@ +package rocket +package config + +import java.io.File +import java.io.FileInputStream +import java.util.Properties +import scala.util.{Properties => SProperties} + +class Config(props: Properties) { + private val msg = "Configuration is missing requested parameter " + def getInt(name: String): Int = Option(props.getProperty(name).toInt).getOrElse(sys.error(msg+name)) + def getString(name: String): String = Option(props.getProperty(name)).getOrElse(sys.error(msg+name)) + def getBoolean(name: String): Boolean = Option(props.getProperty(name).toBoolean).getOrElse(sys.error(msg+name)) + def apply(name: String): Int = getInt(name) +} + +object Config { + + lazy val internal_config = getConfig() + + def apply(name: String) = internal_config(name) + + private def getConfig(): Config = { + + val filePath0 = + SProperties + .envOrNone("ROCKET_CONFIG") + .orElse(SProperties.propOrNone("rocket.config")) + if (filePath0.isEmpty) + Console.err.println(""" + | WARNING: Could not find configuration file to load. + | Options are: + | (1) Set environmental variable ROCKET_CONFIG to the config file path + | (2) Set system property rocket.config to the config file path + | Using default values for config. + """.stripMargin) + + val filePath = + filePath0.flatMap(fp => { + val f = new File(fp) + if (!f.isFile) { + Console.err.println(""" + | WARNING: File '%s' is not a valid file path + | Using default values for config + """.format(fp).stripMargin) + None + } else Some(fp) + }) + + val props = new Properties() + filePath.map(fp => props.load(new FileInputStream(fp))) + new Config(props) + } + +} + diff --git a/rocket/src/main/scala/rocket.config b/rocket/src/main/scala/rocket.config new file mode 100644 index 00000000..65b60ff0 --- /dev/null +++ b/rocket/src/main/scala/rocket.config @@ -0,0 +1 @@ +NWAYS 4 From 8970b635b216d6407ea5a11d5672b7ba5f783b83 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Mon, 15 Oct 2012 16:29:49 -0700 Subject: [PATCH 6/7] improvements to implicit RocketConfiguration parameter --- rocket/src/main/scala/cpu.scala | 8 ++++---- rocket/src/main/scala/dpath.scala | 6 +++--- rocket/src/main/scala/dpath_util.scala | 8 ++++---- rocket/src/main/scala/htif.scala | 4 ++-- rocket/src/main/scala/icache.scala | 2 +- rocket/src/main/scala/nbdcache.scala | 12 ++++++------ rocket/src/main/scala/tile.scala | 2 +- rocket/src/main/scala/top.scala | 4 ++-- 8 files changed, 23 insertions(+), 23 deletions(-) diff --git a/rocket/src/main/scala/cpu.scala b/rocket/src/main/scala/cpu.scala index 8f7f49fc..b9adcd8d 100644 --- a/rocket/src/main/scala/cpu.scala +++ b/rocket/src/main/scala/cpu.scala @@ -5,7 +5,7 @@ import Node._ import Constants._ import hwacha._ -class ioRocket()(implicit conf: Configuration) extends Bundle +class ioRocket(implicit conf: RocketConfiguration) extends Bundle { val host = new ioHTIF() val imem = (new ioImem).flip @@ -13,12 +13,12 @@ class ioRocket()(implicit conf: Configuration) extends Bundle val dmem = new ioHellaCache } -class rocketProc()(implicit conf: Configuration) extends Component +class rocketProc(implicit conf: RocketConfiguration) extends Component { val io = new ioRocket - val ctrl = new rocketCtrl(); - val dpath = new rocketDpath(); + val ctrl = new rocketCtrl + val dpath = new rocketDpath val dtlb = new rocketDTLB(DTLB_ENTRIES); val itlb = new rocketITLB(ITLB_ENTRIES); diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala index fc199520..64e45086 100644 --- a/rocket/src/main/scala/dpath.scala +++ b/rocket/src/main/scala/dpath.scala @@ -12,9 +12,9 @@ class ioDpathImem extends Bundle() val resp_data = Bits(INPUT, 32); } -class ioDpathAll()(implicit conf: Configuration) extends Bundle() +class ioDpathAll(implicit conf: RocketConfiguration) extends Bundle { - val host = new ioHTIF() + val host = new ioHTIF val ctrl = new ioCtrlDpath().flip val dmem = new ioHellaCache val dtlb = new ioDTLB_CPU_req_bundle().asOutput() @@ -28,7 +28,7 @@ class ioDpathAll()(implicit conf: Configuration) extends Bundle() val vec_imul_resp = Bits(INPUT, hwacha.Constants.SZ_XLEN) } -class rocketDpath()(implicit conf: Configuration) extends Component +class rocketDpath(implicit conf: RocketConfiguration) extends Component { val io = new ioDpathAll(); diff --git a/rocket/src/main/scala/dpath_util.scala b/rocket/src/main/scala/dpath_util.scala index 66e6dec9..e0e2b84a 100644 --- a/rocket/src/main/scala/dpath_util.scala +++ b/rocket/src/main/scala/dpath_util.scala @@ -57,9 +57,9 @@ class rocketDpathBTB(entries: Int) extends Component io.target := mux.io.out.toUFix } -class ioDpathPCR()(implicit conf: Configuration) extends Bundle() +class ioDpathPCR(implicit conf: RocketConfiguration) extends Bundle { - val host = new ioHTIF() + val host = new ioHTIF val r = new ioReadPort(); val w = new ioWritePort(); @@ -86,9 +86,9 @@ class ioDpathPCR()(implicit conf: Configuration) extends Bundle() val vec_nfregs = UFix(INPUT, 6) } -class rocketDpathPCR()(implicit conf: Configuration) extends Component +class rocketDpathPCR(implicit conf: RocketConfiguration) extends Component { - val io = new ioDpathPCR(); + val io = new ioDpathPCR val reg_epc = Reg() { UFix() }; val reg_badvaddr = Reg() { UFix() }; diff --git a/rocket/src/main/scala/htif.scala b/rocket/src/main/scala/htif.scala index 761bb59d..5f2a3e35 100644 --- a/rocket/src/main/scala/htif.scala +++ b/rocket/src/main/scala/htif.scala @@ -23,7 +23,7 @@ class PCRReq extends Bundle val data = Bits(width = 64) } -class ioHTIF()(implicit conf: Configuration) extends Bundle +class ioHTIF(implicit conf: RocketConfiguration) extends Bundle { val reset = Bool(INPUT) val debug = new ioDebug @@ -33,7 +33,7 @@ class ioHTIF()(implicit conf: Configuration) extends Bundle val ipi_rep = (new FIFOIO) { Bool() }.flip } -class rocketHTIF(w: Int)(implicit conf: Configuration) extends Component +class rocketHTIF(w: Int)(implicit conf: RocketConfiguration) extends Component { val io = new Bundle { val host = new ioHost(w) diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala index c0fa675e..6b3894ca 100644 --- a/rocket/src/main/scala/icache.scala +++ b/rocket/src/main/scala/icache.scala @@ -28,7 +28,7 @@ class ioRocketICache extends Bundle() // 32 bit wide cpu port, 128 bit wide memory port, 64 byte cachelines // parameters : // lines = # cache lines -class rocketICache(sets: Int, assoc: Int)(implicit conf: Configuration) extends Component +class rocketICache(sets: Int, assoc: Int)(implicit conf: RocketConfiguration) extends Component { val io = new ioRocketICache(); diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index a2f0839a..6c68c302 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -159,7 +159,7 @@ class MetaArrayReq extends Bundle { val data = new MetaData() } -class MSHR(id: Int)(implicit conf: Configuration) extends Component { +class MSHR(id: Int)(implicit conf: RocketConfiguration) extends Component { val io = new Bundle { val req_pri_val = Bool(INPUT) val req_pri_rdy = Bool(OUTPUT) @@ -293,7 +293,7 @@ class MSHR(id: Int)(implicit conf: Configuration) extends Component { io.replay.bits.way_oh := req.way_oh } -class MSHRFile()(implicit conf: Configuration) extends Component { +class MSHRFile(implicit conf: RocketConfiguration) extends Component { val io = new Bundle { val req = (new FIFOIO) { new MSHRReq }.flip val secondary_miss = Bool(OUTPUT) @@ -415,7 +415,7 @@ class MSHRFile()(implicit conf: Configuration) extends Component { } -class WritebackUnit()(implicit conf: Configuration) extends Component { +class WritebackUnit(implicit conf: RocketConfiguration) extends Component { val io = new Bundle { val req = (new FIFOIO) { new WritebackReq() }.flip val probe = (new FIFOIO) { new WritebackReq() }.flip @@ -484,7 +484,7 @@ class WritebackUnit()(implicit conf: Configuration) extends Component { io.probe_rep_data.bits.data := io.data_resp } -class ProbeUnit()(implicit conf: Configuration) extends Component { +class ProbeUnit(implicit conf: RocketConfiguration) extends Component { val io = new Bundle { val req = (new FIFOIO) { new ProbeRequest }.flip val rep = (new FIFOIO) { new ProbeReply } @@ -548,7 +548,7 @@ class ProbeUnit()(implicit conf: Configuration) extends Component { io.wb_req.bits.tag := req.addr >> UFix(IDX_BITS) } -class FlushUnit(lines: Int)(implicit conf: Configuration) extends Component { +class FlushUnit(lines: Int)(implicit conf: RocketConfiguration) extends Component { val io = new Bundle { val req = (new FIFOIO) { Bool() }.flip val meta_req = (new FIFOIO) { new MetaArrayReq() } @@ -748,7 +748,7 @@ class ioHellaCache extends Bundle { val xcpt = (new HellaCacheExceptions).asInput } -class HellaCache()(implicit conf: Configuration) extends Component { +class HellaCache(implicit conf: RocketConfiguration) extends Component { val io = new Bundle { val cpu = (new ioHellaCache).flip val mem = new ioTileLink diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala index 69aef22d..0a37db2a 100644 --- a/rocket/src/main/scala/tile.scala +++ b/rocket/src/main/scala/tile.scala @@ -5,7 +5,7 @@ import Node._ import Constants._ import uncore._ -class Tile(resetSignal: Bool = null)(implicit conf: Configuration) extends Component(resetSignal) +class Tile(resetSignal: Bool = null)(implicit conf: RocketConfiguration) extends Component(resetSignal) { val io = new Bundle { val tilelink = new ioTileLink diff --git a/rocket/src/main/scala/top.scala b/rocket/src/main/scala/top.scala index 7b29021c..df6f084d 100644 --- a/rocket/src/main/scala/top.scala +++ b/rocket/src/main/scala/top.scala @@ -13,7 +13,7 @@ object DummyTopLevelConstants extends rocket.constants.CoherenceConfigConstants } import DummyTopLevelConstants._ -case class Configuration(ntiles: Int, co: CoherencePolicyWithUncached) +case class RocketConfiguration(ntiles: Int, co: CoherencePolicyWithUncached) class Top extends Component { @@ -24,7 +24,7 @@ class Top extends Component if(ENABLE_CLEAN_EXCLUSIVE) new MEICoherence else new MICoherence } - implicit val conf = Configuration(NTILES, co) + implicit val conf = RocketConfiguration(NTILES, co) val io = new Bundle { val debug = new ioDebug From 6cff1c13d861483ed1ef3c2137187241eaa94458 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Tue, 16 Oct 2012 14:22:23 -0700 Subject: [PATCH 7/7] Refer to traits moved to uncore, add UncoreConfiguration to top --- rocket/src/main/scala/consts.scala | 63 +++-------------------------- rocket/src/main/scala/package.scala | 6 +-- rocket/src/main/scala/top.scala | 7 ++-- 3 files changed, 12 insertions(+), 64 deletions(-) diff --git a/rocket/src/main/scala/consts.scala b/rocket/src/main/scala/consts.scala index 9ec91845..294e4052 100644 --- a/rocket/src/main/scala/consts.scala +++ b/rocket/src/main/scala/consts.scala @@ -4,53 +4,6 @@ package constants import Chisel._ import scala.math._ -abstract trait MulticoreConstants { - val NTILES: Int - val TILE_ID_BITS = log2Up(NTILES)+1 -} - -abstract trait CoherenceConfigConstants { - val ENABLE_SHARING: Boolean - val ENABLE_CLEAN_EXCLUSIVE: Boolean -} - -trait UncoreConstants { - val NGLOBAL_XACTS = 8 - val GLOBAL_XACT_ID_BITS = log2Up(NGLOBAL_XACTS) -} - -trait TileLinkTypeConstants { - val X_INIT_TYPE_MAX_BITS = 2 - val X_REP_TYPE_MAX_BITS = 3 - val P_REQ_TYPE_MAX_BITS = 2 - val P_REP_TYPE_MAX_BITS = 3 -} - -trait TileLinkSizeConstants extends - RocketDcacheConstants with - TileLinkTypeConstants -{ - val TILE_XACT_ID_BITS = log2Up(NMSHR)+3 - val X_INIT_WRITE_MASK_BITS = OFFSET_BITS - val X_INIT_SUBWORD_ADDR_BITS = log2Up(OFFSET_BITS) - val X_INIT_ATOMIC_OP_BITS = 4 -} - -trait HTIFConstants { - val HTIF_WIDTH = 16 -} - -trait MemoryInterfaceConstants extends - HTIFConstants with - UncoreConstants with - TileLinkSizeConstants -{ - val MEM_TAG_BITS = max(TILE_XACT_ID_BITS, GLOBAL_XACT_ID_BITS) - val MEM_DATA_BITS = 128 - val REFILL_CYCLES = (1 << OFFSET_BITS)*8/MEM_DATA_BITS - val MEM_BACKUP_WIDTH = HTIF_WIDTH -} - abstract trait TileConfigConstants { def HAVE_RVC: Boolean def HAVE_FPU: Boolean @@ -219,25 +172,19 @@ trait InterruptConstants { val IRQ_TIMER = 7 } -trait AddressConstants { - val PADDR_BITS = 40; - val VADDR_BITS = 43; - val PGIDX_BITS = 13; - val PPN_BITS = PADDR_BITS-PGIDX_BITS; - val VPN_BITS = VADDR_BITS-PGIDX_BITS; - val ASID_BITS = 7; - val PERM_BITS = 6; -} - -abstract trait RocketDcacheConstants extends ArbiterConstants with AddressConstants { +abstract trait RocketDcacheConstants extends ArbiterConstants with uncore.constants.AddressConstants { val CPU_DATA_BITS = 64; val CPU_TAG_BITS = 9; val DCACHE_TAG_BITS = log2Up(DCACHE_PORTS) + CPU_TAG_BITS val LG_REFILL_WIDTH = 4; // log2(cache bus width in bytes) val NMSHR = if (HAVE_VEC) 4 else 2 // number of primary misses + require(log2Up(NMSHR)+3 <= uncore.Constants.TILE_XACT_ID_BITS) val NRPQ = 16; // number of secondary misses val NSDQ = 17; // number of secondary stores/AMOs val OFFSET_BITS = 6; // log2(cache line size in bytes) + require(OFFSET_BITS == log2Up(uncore.Constants.CACHE_DATA_SIZE_IN_BYTES)) + require(OFFSET_BITS <= uncore.Constants.X_INIT_WRITE_MASK_BITS) + require(log2Up(OFFSET_BITS) <= uncore.Constants.X_INIT_SUBWORD_ADDR_BITS) val IDX_BITS = 7; val TAG_BITS = PADDR_BITS - OFFSET_BITS - IDX_BITS; val NWAYS = 4 diff --git a/rocket/src/main/scala/package.scala b/rocket/src/main/scala/package.scala index aaa06dcd..28fdcfad 100644 --- a/rocket/src/main/scala/package.scala +++ b/rocket/src/main/scala/package.scala @@ -8,13 +8,13 @@ import scala.math._ // package object rocket and remove import Constants._'s from other files object Constants extends ScalarOpConstants with - MemoryOpConstants with + uncore.constants.MemoryOpConstants with PCRConstants with InterruptConstants with - AddressConstants with + RocketDcacheConstants with VectorOpConstants with TLBConstants with - MemoryInterfaceConstants + uncore.constants.MemoryInterfaceConstants { def HAVE_RVC = false def HAVE_FPU = true diff --git a/rocket/src/main/scala/top.scala b/rocket/src/main/scala/top.scala index df6f084d..9e051d0e 100644 --- a/rocket/src/main/scala/top.scala +++ b/rocket/src/main/scala/top.scala @@ -6,7 +6,7 @@ import Constants._ import uncore._ import collection.mutable.ArrayBuffer -object DummyTopLevelConstants extends rocket.constants.CoherenceConfigConstants with rocket.constants.MulticoreConstants { +object DummyTopLevelConstants extends uncore.constants.CoherenceConfigConstants { val NTILES = 1 val ENABLE_SHARING = true val ENABLE_CLEAN_EXCLUSIVE = true @@ -24,7 +24,8 @@ class Top extends Component if(ENABLE_CLEAN_EXCLUSIVE) new MEICoherence else new MICoherence } - implicit val conf = RocketConfiguration(NTILES, co) + implicit val rconf = RocketConfiguration(NTILES, co) + implicit val uconf = UncoreConfiguration(NTILES+1, log2Up(NTILES)+1) val io = new Bundle { val debug = new ioDebug @@ -33,7 +34,7 @@ class Top extends Component } val htif = new rocketHTIF(HTIF_WIDTH) - val hub = new CoherenceHubBroadcast(NTILES+1, co) + val hub = new CoherenceHubBroadcast(co) hub.io.tiles(NTILES) <> htif.io.mem io.host <> htif.io.host