riscv/rocket-chip
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Merged consts-as-traits

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This commit is contained in:
Henry Cook
2012-10-16 16:32:35 -07:00
parent b9a2af697d 6cff1c13d8
commit 88ac5af181
20 changed files with 357 additions and 272 deletions
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17
rocket/src/main/scala/tile.scala
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@ -5,7 +5,7 @@ import Node._
import Constants._
import uncore._
class Tile(co: CoherencePolicyWithUncached, resetSignal: Bool = null) extends Component(resetSignal)
class Tile(resetSignal: Bool = null)(implicit conf: RocketConfiguration) extends Component(resetSignal)
{
val io = new Bundle {
val tilelink = new ioTileLink
@ -13,12 +13,12 @@ class Tile(co: CoherencePolicyWithUncached, resetSignal: Bool = null) extends Co
}
val cpu = new rocketProc
val icache = new Frontend(ICacheConfig(co, 128, 4)) // 128 sets x 4 ways (32KB)
val dcache = new HellaCache(co)
val icache = new Frontend(ICacheConfig(128, 4)) // 128 sets x 4 ways (32KB)
val dcache = new HellaCache
val arbiter = new rocketMemArbiter(2 + (if (HAVE_VEC) 1 else 0))
arbiter.io.requestor(0) <> dcache.io.mem
arbiter.io.requestor(1) <> icache.io.mem
val arbiter = new rocketMemArbiter(DMEM_PORTS)
arbiter.io.requestor(DMEM_DCACHE) <> dcache.io.mem
arbiter.io.requestor(DMEM_ICACHE) <> icache.io.mem
io.tilelink.xact_init <> arbiter.io.mem.xact_init
io.tilelink.xact_init_data <> dcache.io.mem.xact_init_data
@ -31,13 +31,12 @@ class Tile(co: CoherencePolicyWithUncached, resetSignal: Bool = null) extends Co
if (HAVE_VEC)
{
val vicache = new Frontend(ICacheConfig(co, 128, 1)) // 128 sets x 1 ways (8KB)
arbiter.io.requestor(2) <> vicache.io.mem
val vicache = new Frontend(ICacheConfig(128, 1)) // 128 sets x 1 ways (8KB)
arbiter.io.requestor(DMEM_VICACHE) <> vicache.io.mem
cpu.io.vimem <> vicache.io.cpu
}
cpu.io.host <> io.host
cpu.io.imem <> icache.io.cpu
cpu.io.dmem <> dcache.io.cpu
}