riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

writes of PC weren't being sign extended

Browse Source
This commit is contained in:
Rimas Avizienis 2011-11-15 18:07:36 -08:00
parent fc0f20643a
commit 886857fa47
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
rocket/src/main/scala/dpath.scala
View File

@ -373,7 +373,7 @@ class rocketDpath extends Component
// writeback select mux // writeback select mux
ex_wdata := ex_wdata :=
Mux(ex_reg_ctrl_ll_wb || ex_reg_ctrl_wen_pcr, ex_reg_rs1, Mux(ex_reg_ctrl_ll_wb || ex_reg_ctrl_wen_pcr, ex_reg_rs1,
Mux(ex_reg_ctrl_sel_wb === WB_PC, ex_reg_pc_plus4, Mux(ex_reg_ctrl_sel_wb === WB_PC, Cat(Fill(64-VADDR_BITS, ex_reg_pc_plus4(VADDR_BITS-1)), ex_reg_pc_plus4),
Mux(ex_reg_ctrl_sel_wb === WB_ALU, ex_alu_out, Mux(ex_reg_ctrl_sel_wb === WB_ALU, ex_alu_out,
Mux(ex_reg_ctrl_sel_wb === WB_PCR, ex_pcr, Mux(ex_reg_ctrl_sel_wb === WB_PCR, ex_pcr,
Bits(0, 64))))).toBits; Bits(0, 64))))).toBits;