riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Use PseudoLRU in BTB when possible (for powers of two)

Browse Source
This commit is contained in:
Andrew Waterman 2016-09-12 16:52:03 -07:00
parent 266a2f24bd
commit 88440ebf89
1 changed files with 11 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
src/main/scala/rocket/btb.scala
View File

@ -7,6 +7,7 @@ import junctions._
import cde.{Parameters, Field} import cde.{Parameters, Field}
import Util._ import Util._
import uncore.util._ import uncore.util._
import uncore.agents.PseudoLRU
case object BtbKey extends Field[BtbParameters] case object BtbKey extends Field[BtbParameters]
@ -180,7 +181,16 @@ class BTB(implicit p: Parameters) extends BtbModule {
val updateHits = tagMatch(r_btb_update.bits.pc, updatePageHit) val updateHits = tagMatch(r_btb_update.bits.pc, updatePageHit)
val updateHit = if (updatesOutOfOrder) updateHits.orR else r_btb_update.bits.prediction.valid val updateHit = if (updatesOutOfOrder) updateHits.orR else r_btb_update.bits.prediction.valid
val updateHitAddr = if (updatesOutOfOrder) OHToUInt(updateHits) else r_btb_update.bits.prediction.bits.entry val updateHitAddr = if (updatesOutOfOrder) OHToUInt(updateHits) else r_btb_update.bits.prediction.bits.entry
val nextRepl = Counter(r_btb_update.valid && !updateHit, entries)._1
// we'd prefer PseudoLRU replacement, but it only works for powers of 2
val nextRepl =
if (!isPow2(entries)) {
Counter(r_btb_update.valid && !updateHit, entries)._1
} else {
val plru = new PseudoLRU(entries)
when (hits.orR) { plru.access(OHToUInt(hits)) }
plru.replace
}
val useUpdatePageHit = updatePageHit.orR val useUpdatePageHit = updatePageHit.orR
val usePageHit = pageHit.orR val usePageHit = pageHit.orR