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Fix HastiTestSRAM can't R/W byte when HSIZE is 0 (#563)

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Leway Colin 2017-02-25 02:37:26 +08:00 committed by Henry Cook
parent 027d6247b6
commit 87d909e996
1 changed files with 1 additions and 1 deletions
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src/main/scala/junctions/hasti.scala
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@ -470,7 +470,7 @@ class HastiTestSRAM(depth: Int)(implicit p: Parameters) extends HastiModule()(p)
// Calculate the bitmask of which bytes are being accessed // Calculate the bitmask of which bytes are being accessed
val mask_decode = Vec.tabulate(hastiAlignment+1) (UInt(_) <= io.hsize) val mask_decode = Vec.tabulate(hastiAlignment+1) (UInt(_) <= io.hsize)
val mask_wide = Vec.tabulate(hastiDataBytes) { i => mask_decode(log2Up(i+1)) } val mask_wide = Vec.tabulate(hastiDataBytes) { i => mask_decode(log2Ceil(i+1)) }
val mask_shift = if (hastiAlignment == 0) UInt(1) else val mask_shift = if (hastiAlignment == 0) UInt(1) else
mask_wide.asUInt() << io.haddr(hastiAlignment-1,0) mask_wide.asUInt() << io.haddr(hastiAlignment-1,0)