From 87d909e9966097e590945cb6a06c01e91bdfa45b Mon Sep 17 00:00:00 2001 From: Leway Colin Date: Sat, 25 Feb 2017 02:37:26 +0800 Subject: [PATCH] Fix HastiTestSRAM can't R/W byte when HSIZE is 0 (#563) --- src/main/scala/junctions/hasti.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/junctions/hasti.scala b/src/main/scala/junctions/hasti.scala index 3d5c075d..6befbadc 100644 --- a/src/main/scala/junctions/hasti.scala +++ b/src/main/scala/junctions/hasti.scala @@ -470,7 +470,7 @@ class HastiTestSRAM(depth: Int)(implicit p: Parameters) extends HastiModule()(p) // Calculate the bitmask of which bytes are being accessed val mask_decode = Vec.tabulate(hastiAlignment+1) (UInt(_) <= io.hsize) - val mask_wide = Vec.tabulate(hastiDataBytes) { i => mask_decode(log2Up(i+1)) } + val mask_wide = Vec.tabulate(hastiDataBytes) { i => mask_decode(log2Ceil(i+1)) } val mask_shift = if (hastiAlignment == 0) UInt(1) else mask_wide.asUInt() << io.haddr(hastiAlignment-1,0)