riscv/rocket-chip
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Removed defunct ioDmem

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This commit is contained in:
Henry Cook 2012-05-07 17:28:18 -07:00
parent b851f1b34c
commit 87cbae2c8a
2 changed files with 4 additions and 26 deletions
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2
rocket/src/main/scala/cpu.scala
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@ -118,10 +118,10 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
io.imem.itlb_miss := itlb.io.cpu.resp_miss; io.imem.itlb_miss := itlb.io.cpu.resp_miss;
// connect arbiter to ctrl+dpath+DTLB // connect arbiter to ctrl+dpath+DTLB
//TODO: views on nested bundles?
arb.io.requestor(DMEM_CPU).resp <> ctrl.io.dmem.resp arb.io.requestor(DMEM_CPU).resp <> ctrl.io.dmem.resp
arb.io.requestor(DMEM_CPU).xcpt <> ctrl.io.dmem.xcpt arb.io.requestor(DMEM_CPU).xcpt <> ctrl.io.dmem.xcpt
arb.io.requestor(DMEM_CPU).resp <> dpath.io.dmem.resp arb.io.requestor(DMEM_CPU).resp <> dpath.io.dmem.resp
//TODO: views on nested bundles?
arb.io.requestor(DMEM_CPU).req.valid := ctrl.io.dmem.req.valid arb.io.requestor(DMEM_CPU).req.valid := ctrl.io.dmem.req.valid
ctrl.io.dmem.req.ready := arb.io.requestor(DMEM_CPU).req.ready ctrl.io.dmem.req.ready := arb.io.requestor(DMEM_CPU).req.ready
arb.io.requestor(DMEM_CPU).req.bits.kill := ctrl.io.dmem.req.bits.kill arb.io.requestor(DMEM_CPU).req.bits.kill := ctrl.io.dmem.req.bits.kill

28
rocket/src/main/scala/nbdcache.scala
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@ -717,13 +717,13 @@ class AMOALU extends Component {
} }
class HellaCacheReq extends Bundle { class HellaCacheReq extends Bundle {
val cmd = Bits(width = 4) val kill = Bool()
val typ = Bits(width = 3) val typ = Bits(width = 3)
val idx = Bits(width = PGIDX_BITS) val idx = Bits(width = PGIDX_BITS)
val ppn = Bits(width = PPN_BITS) val ppn = Bits(width = PPN_BITS)
val data = Bits(width = 64) val data = Bits(width = 64)
val kill = Bool()
val tag = Bits(width = DCACHE_TAG_BITS) val tag = Bits(width = DCACHE_TAG_BITS)
val cmd = Bits(width = 4)
} }
class HellaCacheResp extends Bundle { class HellaCacheResp extends Bundle {
@ -745,35 +745,13 @@ class HellaCacheExceptions extends Bundle {
val ma = new AlignmentExceptions val ma = new AlignmentExceptions
} }
// interface between D$ and processor/DTLB
class ioHellaCache extends Bundle { class ioHellaCache extends Bundle {
val req = (new ioDecoupled){ new HellaCacheReq } val req = (new ioDecoupled){ new HellaCacheReq }
val resp = (new ioPipe){ new HellaCacheResp }.flip val resp = (new ioPipe){ new HellaCacheResp }.flip
val xcpt = (new HellaCacheExceptions).asInput val xcpt = (new HellaCacheExceptions).asInput
} }
// interface between D$ and processor/DTLB
class ioDmem(view: List[String] = null) extends Bundle(view) {
val req_kill = Bool(INPUT);
val req_val = Bool(INPUT);
val req_rdy = Bool(OUTPUT);
val req_cmd = Bits(4, INPUT);
val req_type = Bits(3, INPUT);
val req_idx = Bits(PGIDX_BITS, INPUT);
val req_ppn = Bits(PPN_BITS, INPUT);
val req_data = Bits(64, INPUT);
val req_tag = Bits(DCACHE_TAG_BITS, INPUT);
val xcpt_ma_ld = Bool(OUTPUT); // misaligned load
val xcpt_ma_st = Bool(OUTPUT); // misaligned store
val resp_miss = Bool(OUTPUT);
val resp_nack = Bool(OUTPUT);
val resp_val = Bool(OUTPUT);
val resp_replay = Bool(OUTPUT);
val resp_type = Bits(3, OUTPUT);
val resp_data = Bits(64, OUTPUT);
val resp_data_subword = Bits(64, OUTPUT);
val resp_tag = Bits(DCACHE_TAG_BITS, OUTPUT);
}
class HellaCache(co: CoherencePolicy) extends Component { class HellaCache(co: CoherencePolicy) extends Component {
val io = new Bundle { val io = new Bundle {
val cpu = (new ioHellaCache).flip val cpu = (new ioHellaCache).flip