From 87cbae2c8ace6861ea057e7765e1da6c75437a35 Mon Sep 17 00:00:00 2001
From: Henry Cook <hcook@s144.Millennium.Berkeley.EDU>
Date: Mon, 7 May 2012 17:28:18 -0700
Subject: [PATCH] Removed defunct ioDmem

---
 rocket/src/main/scala/cpu.scala      |  2 +-
 rocket/src/main/scala/nbdcache.scala | 28 +++-------------------------
 2 files changed, 4 insertions(+), 26 deletions(-)

diff --git a/rocket/src/main/scala/cpu.scala b/rocket/src/main/scala/cpu.scala
index d1842e21..0799b8e0 100644
--- a/rocket/src/main/scala/cpu.scala
+++ b/rocket/src/main/scala/cpu.scala
@@ -118,10 +118,10 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
   io.imem.itlb_miss       := itlb.io.cpu.resp_miss;
 
   // connect arbiter to ctrl+dpath+DTLB
+  //TODO: views on nested bundles?
   arb.io.requestor(DMEM_CPU).resp <> ctrl.io.dmem.resp
   arb.io.requestor(DMEM_CPU).xcpt <> ctrl.io.dmem.xcpt
   arb.io.requestor(DMEM_CPU).resp <> dpath.io.dmem.resp
-  //TODO: views on nested bundles?
   arb.io.requestor(DMEM_CPU).req.valid     := ctrl.io.dmem.req.valid
   ctrl.io.dmem.req.ready := arb.io.requestor(DMEM_CPU).req.ready
   arb.io.requestor(DMEM_CPU).req.bits.kill := ctrl.io.dmem.req.bits.kill
diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index c713b6f3..c2e93e8e 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -717,13 +717,13 @@ class AMOALU extends Component {
 }
 
 class HellaCacheReq extends Bundle {
-  val cmd  = Bits(width = 4)
+  val kill = Bool()
   val typ  = Bits(width = 3)
   val idx  = Bits(width = PGIDX_BITS)
   val ppn  = Bits(width = PPN_BITS)
   val data = Bits(width = 64)
-  val kill = Bool()
   val tag  = Bits(width = DCACHE_TAG_BITS)
+  val cmd  = Bits(width = 4)
 }
 
 class HellaCacheResp extends Bundle {
@@ -745,35 +745,13 @@ class HellaCacheExceptions extends Bundle {
   val ma = new AlignmentExceptions
 }
 
+// interface between D$ and processor/DTLB
 class ioHellaCache extends Bundle {
   val req = (new ioDecoupled){ new HellaCacheReq }
   val resp = (new ioPipe){ new HellaCacheResp }.flip
   val xcpt = (new HellaCacheExceptions).asInput
 }
 
-// interface between D$ and processor/DTLB
-class ioDmem(view: List[String] = null) extends Bundle(view) {
-  val req_kill  = Bool(INPUT);
-  val req_val   = Bool(INPUT);
-  val req_rdy   = Bool(OUTPUT);
-  val req_cmd   = Bits(4, INPUT);
-  val req_type  = Bits(3, INPUT);
-  val req_idx   = Bits(PGIDX_BITS, INPUT);
-  val req_ppn   = Bits(PPN_BITS, INPUT);
-  val req_data  = Bits(64, INPUT);
-  val req_tag   = Bits(DCACHE_TAG_BITS, INPUT);
-  val xcpt_ma_ld  = Bool(OUTPUT); // misaligned load
-  val xcpt_ma_st = Bool(OUTPUT); // misaligned store
-  val resp_miss = Bool(OUTPUT);
-  val resp_nack = Bool(OUTPUT);
-  val resp_val  = Bool(OUTPUT);
-  val resp_replay = Bool(OUTPUT);
-  val resp_type = Bits(3, OUTPUT);
-  val resp_data = Bits(64, OUTPUT);
-  val resp_data_subword = Bits(64, OUTPUT);
-  val resp_tag  = Bits(DCACHE_TAG_BITS, OUTPUT);
-}
- 
 class HellaCache(co: CoherencePolicy) extends Component {
   val io = new Bundle {
     val cpu = (new ioHellaCache).flip