riscv/rocket-chip
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Exit from testbench, not C code

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Otherwise, we don't get coverage data from the simulator.
This commit is contained in:
Andrew Waterman 2016-06-23 20:54:07 -07:00
parent 4cd709c516
commit 87a4858aa6
3 changed files with 3 additions and 9 deletions
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5
csrc/vcs_main.rocketTestHarness.cc
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@ -21,11 +21,6 @@ static const char* loadmem;
static bool dramsim = false; static bool dramsim = false;
static int memory_channel_mux_select = 0; static int memory_channel_mux_select = 0;
void do_exit(vc_handle failure)
{
exit(vc_getScalar(failure));
}
int main(int argc, char** argv) int main(int argc, char** argv)
{ {
for (int i = 1; i < argc; i++) for (int i = 1; i < argc; i++)

1
vsim/Makefrag
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@ -41,6 +41,7 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
-e vcs_main \ -e vcs_main \
$(RISCV)/lib/libfesvr.so \ $(RISCV)/lib/libfesvr.so \
$(sim_dir)/libdramsim.a \ $(sim_dir)/libdramsim.a \
-sverilog \
+incdir+$(generated_dir) \ +incdir+$(generated_dir) \
+define+CLOCK_PERIOD=0.5 $(sim_vsrcs) $(sim_csrcs) \ +define+CLOCK_PERIOD=0.5 $(sim_vsrcs) $(sim_csrcs) \
+define+PRINTF_COND=$(TB).printf_cond \ +define+PRINTF_COND=$(TB).printf_cond \

6
vsrc/rocketTestHarness.v
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@ -1,7 +1,5 @@
// See LICENSE for license details. // See LICENSE for license details.
extern "A" void do_exit(input reg failure);
extern "A" void debug_tick extern "A" void debug_tick
( (
output reg debug_req_valid, output reg debug_req_valid,
@ -159,7 +157,7 @@ module rocketTestHarness;
begin begin
$fdisplay(stderr, "*** FAILED *** (%s) after %d simulation cycles", reason, trace_count); $fdisplay(stderr, "*** FAILED *** (%s) after %d simulation cycles", reason, trace_count);
`VCDPLUSCLOSE `VCDPLUSCLOSE
do_exit(1'b1); $fatal;
end end
if (exit == 1) if (exit == 1)
@ -167,7 +165,7 @@ module rocketTestHarness;
if (verbose) if (verbose)
$fdisplay(stderr, "Completed after %d simulation cycles", trace_count); $fdisplay(stderr, "Completed after %d simulation cycles", trace_count);
`VCDPLUSCLOSE `VCDPLUSCLOSE
do_exit(1'b0); $finish;
end end
end end