diff --git a/csrc/vcs_main.rocketTestHarness.cc b/csrc/vcs_main.rocketTestHarness.cc
index 3989489f..77ae35a5 100644
--- a/csrc/vcs_main.rocketTestHarness.cc
+++ b/csrc/vcs_main.rocketTestHarness.cc
@@ -21,11 +21,6 @@ static const char* loadmem;
 static bool dramsim = false;
 static int memory_channel_mux_select = 0;
 
-void do_exit(vc_handle failure)
-{
-  exit(vc_getScalar(failure));
-}
-
 int main(int argc, char** argv)
 {
   for (int i = 1; i < argc; i++)
diff --git a/vsim/Makefrag b/vsim/Makefrag
index f0240edf..592728d2 100644
--- a/vsim/Makefrag
+++ b/vsim/Makefrag
@@ -41,6 +41,7 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
 	-e vcs_main \
 	$(RISCV)/lib/libfesvr.so \
 	$(sim_dir)/libdramsim.a \
+	-sverilog \
 	+incdir+$(generated_dir) \
 	+define+CLOCK_PERIOD=0.5 $(sim_vsrcs) $(sim_csrcs) \
 	+define+PRINTF_COND=$(TB).printf_cond \
diff --git a/vsrc/rocketTestHarness.v b/vsrc/rocketTestHarness.v
index 333ca9c4..6b8b1fc8 100644
--- a/vsrc/rocketTestHarness.v
+++ b/vsrc/rocketTestHarness.v
@@ -1,7 +1,5 @@
 // See LICENSE for license details.
 
-extern "A" void do_exit(input reg failure);
-
 extern "A" void debug_tick
 (
   output reg        debug_req_valid,
@@ -159,7 +157,7 @@ module rocketTestHarness;
     begin
       $fdisplay(stderr, "*** FAILED *** (%s) after %d simulation cycles", reason, trace_count);
       `VCDPLUSCLOSE
-      do_exit(1'b1);
+      $fatal;
     end
 
     if (exit == 1)
@@ -167,7 +165,7 @@ module rocketTestHarness;
       if (verbose)
         $fdisplay(stderr, "Completed after %d simulation cycles", trace_count);
       `VCDPLUSCLOSE
-      do_exit(1'b0);
+      $finish;
     end
   end