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RegFieldDesc: Add utilities for generating and describing registers at the same time.

This commit is contained in:
Megan Wachs 2018-03-05 11:22:24 -08:00
parent 644ba6dafa
commit 878a357a0d

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// See LICENSE for license details.
package freechips.rocketchip.util
import Chisel._
import chisel3.experimental._
import chisel3.{Input, Output}
import freechips.rocketchip.regmapper.{RegFieldDesc}
object DescribedReg {
import freechips.rocketchip.regmapper.RegFieldAccessType._
def apply[T <: Data](
gen: => T,
name: String,
desc: String,
reset: Option[T],
access: RegFieldAccessType = RW,
enumerations: Map[BigInt, (String, String)] = Map()): (T, RegFieldDesc) = {
val rdesc = RegFieldDesc(name, desc, None, None,
access, reset.map{_.litValue}, enumerations)
val reg = reset.map{i => RegInit(i)}.getOrElse(Reg(gen))
reg.suggestName(name + "_reg")
(reg, rdesc)
}
def async(
width: Int,
name: String,
desc: String,
reset: Int,
access: RegFieldAccessType = RW,
enumerations: Map[BigInt, (String, String)] = Map()): (SimpleRegIO, RegFieldDesc) = {
val rdesc = RegFieldDesc(name, desc, None, None,
access, Some(reset), enumerations)
val reg = Module(new AsyncResetRegVec(w = width, init = reset))
reg.suggestName(name + "_reg")
(reg.io, rdesc)
}
}