riscv/rocket-chip
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diplomacy: provide a val name for all LazyModule constructions

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This commit is contained in:
Wesley W. Terpstra
2017-12-01 11:27:54 -08:00
parent a3e44375c6
commit 8781d2b2e7
40 changed files with 242 additions and 78 deletions
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11
src/main/scala/tilelink/Xbar.scala
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@ -205,7 +205,10 @@ class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Parame
object TLXbar
{
def apply(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Parameters): TLNode =
LazyModule(new TLXbar(policy)).node
{
val xbar = LazyModule(new TLXbar(policy))
xbar.node
}
def mapInputIds (ports: Seq[TLClientPortParameters ]) = assignRanges(ports.map(_.endSourceId)).map(_.get)
def mapOutputIds(ports: Seq[TLManagerPortParameters]) = assignRanges(ports.map(_.endSinkId))
@ -267,7 +270,8 @@ class TLRAMXbar(nManagers: Int, txns: Int)(implicit p: Parameters) extends LazyM
}
class TLRAMXbarTest(nManagers: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
io.finished := Module(LazyModule(new TLRAMXbar(nManagers,txns)).module).io.finished
val dut = Module(LazyModule(new TLRAMXbar(nManagers,txns)).module)
io.finished := dut.io.finished
}
class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Parameters) extends LazyModule {
@ -290,5 +294,6 @@ class TLMulticlientXbar(nManagers: Int, nClients: Int, txns: Int)(implicit p: Pa
}
class TLMulticlientXbarTest(nManagers: Int, nClients: Int, txns: Int = 5000, timeout: Int = 500000)(implicit p: Parameters) extends UnitTest(timeout) {
io.finished := Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module).io.finished
val dut = Module(LazyModule(new TLMulticlientXbar(nManagers, nClients, txns)).module)
io.finished := dut.io.finished
}