riscv/rocket-chip
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diplomacy: provide a val name for all LazyModule constructions

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This commit is contained in:
Wesley W. Terpstra
2017-12-01 11:27:54 -08:00
parent a3e44375c6
commit 8781d2b2e7
40 changed files with 242 additions and 78 deletions
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5
src/main/scala/tilelink/RAMModel.scala
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@ -334,7 +334,10 @@ class TLRAMModel(log: String = "", ignoreErrorData: Boolean = false)(implicit p:
object TLRAMModel
{
def apply(log: String = "", ignoreErrorData: Boolean = false)(implicit p: Parameters): TLNode =
LazyModule(new TLRAMModel(log, ignoreErrorData)).node
{
val model = LazyModule(new TLRAMModel(log, ignoreErrorData))
model.node
}
case class MonitorParameters(addressBits: Int, sizeBits: Int)