riscv/rocket-chip
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diplomacy: provide a val name for all LazyModule constructions

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This commit is contained in:
Wesley W. Terpstra
2017-12-01 11:27:54 -08:00
parent a3e44375c6
commit 8781d2b2e7
40 changed files with 242 additions and 78 deletions
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12
src/main/scala/interrupts/Crossing.scala
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@ -21,7 +21,11 @@ class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule
object IntSyncCrossingSource
{
def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = LazyModule(new IntSyncCrossingSource(alreadyRegistered)).node
def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) =
{
val intsource = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
intsource.node
}
}
@ -54,5 +58,9 @@ class IntSyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyMod
object IntSyncCrossingSink
{
def apply(sync: Int = 3)(implicit p: Parameters) = LazyModule(new IntSyncCrossingSink(sync)).node
def apply(sync: Int = 3)(implicit p: Parameters) =
{
val intsink = LazyModule(new IntSyncCrossingSink(sync))
intsink.node
}
}