riscv/rocket-chip
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diplomacy: provide a val name for all LazyModule constructions

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This commit is contained in:
Wesley W. Terpstra
2017-12-01 11:27:54 -08:00
parent a3e44375c6
commit 8781d2b2e7
40 changed files with 242 additions and 78 deletions
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6
src/main/scala/amba/axi4/Xbar.scala
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@ -205,7 +205,11 @@ object AXI4Xbar
def apply(
arbitrationPolicy: TLArbiter.Policy = TLArbiter.roundRobin,
maxFlightPerId: Int = 7,
awQueueDepth: Int = 2)(implicit p: Parameters) = LazyModule(new AXI4Xbar(arbitrationPolicy, maxFlightPerId, awQueueDepth)).node
awQueueDepth: Int = 2)(implicit p: Parameters) =
{
val axi4xbar = LazyModule(new AXI4Xbar(arbitrationPolicy, maxFlightPerId, awQueueDepth))
axi4xbar.node
}
def mapInputIds(ports: Seq[AXI4MasterPortParameters]) = TLXbar.assignRanges(ports.map(_.endId)).map(_.get)