riscv/rocket-chip
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refactored vector tlb

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This commit is contained in:
Yunsup Lee
2012-11-06 23:53:52 -08:00
parent 9a02298f6f
commit 8764fe786a
3 changed files with 4 additions and 70 deletions
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13
rocket/src/main/scala/core.scala
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@ -44,18 +44,13 @@ class Core(implicit conf: RocketConfiguration) extends Component
if (HAVE_VEC) {
val vu = new vu()
val vdtlb = new rocketTLB(8)
val vdtlb = new TLB(8)
ptw += vdtlb.io.ptw
vdtlb.io.cpu_req <> vu.io.vec_tlb_req
vu.io.vec_tlb_resp := vdtlb.io.cpu_resp
vu.io.vec_tlb_resp.xcpt_pf := Bool(false)
vdtlb.io <> vu.io.vec_tlb
val pftlb = new rocketTLB(2)
pftlb.io.cpu_req <> vu.io.vec_pftlb_req
val pftlb = new TLB(2)
pftlb.io <> vu.io.vec_pftlb
ptw += pftlb.io.ptw
vu.io.vec_pftlb_resp := pftlb.io.cpu_resp
vu.io.vec_pftlb_resp.xcpt_ld := Bool(false)
vu.io.vec_pftlb_resp.xcpt_st := Bool(false)
dpath.io.vec_ctrl <> ctrl.io.vec_dpath