riscv/rocket-chip
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refactor cpu/i$/d$ into Tile (rather than Top)

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This commit is contained in:
Andrew Waterman
2012-03-24 16:56:59 -07:00
parent 3a487ac89b
commit 86d56ff67b
7 changed files with 59 additions and 47 deletions
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7
rocket/src/main/scala/cpu.scala
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@ -5,14 +5,8 @@ import Node._;
import Constants._;
import hwacha._
class ioDebug(view: List[String] = null) extends Bundle(view)
{
val error_mode = Bool(OUTPUT);
}
class ioRocket extends Bundle()
{
val debug = new ioDebug();
val host = new ioHTIF();
val imem = new ioImem().flip
val vimem = new ioImem().flip
@ -107,7 +101,6 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
ctrl.io.dpath <> dpath.io.ctrl;
dpath.io.host <> io.host;
dpath.io.debug <> io.debug;
// FIXME: try to make this more compact