riscv/rocket-chip
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refactor cpu/i$/d$ into Tile (rather than Top)

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This commit is contained in:
Andrew Waterman
2012-03-24 16:56:59 -07:00
parent 3a487ac89b
commit 86d56ff67b
7 changed files with 59 additions and 47 deletions
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2
rocket/src/main/scala/consts.scala
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@ -7,7 +7,7 @@ object Constants
{
val HAVE_RVC = false
val HAVE_FPU = true
val HAVE_VEC = true
val HAVE_VEC = false
val BR_N = UFix(0, 4);
val BR_EQ = UFix(1, 4);