riscv/rocket-chip
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Factored out Rocket specifics from CoreParameters

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- Added new RocketCoreParameters
   - Other cores using Rocket as a library will no longer conflict against
      Rocket's requires().
This commit is contained in:
Christopher Celio 2014-09-25 18:52:58 -07:00
parent 8eb64205f5
commit 868e747656
1 changed files with 7 additions and 2 deletions
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9
rocket/src/main/scala/core.scala
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@ -28,10 +28,15 @@ abstract trait CoreParameters extends UsesParameters {
val coreMaxAddrBits = math.max(params(PPNBits),params(VPNBits)+1) + params(PgIdxBits) val coreMaxAddrBits = math.max(params(PPNBits),params(VPNBits)+1) + params(PgIdxBits)
if(params(FastLoadByte)) require(params(FastLoadWord)) if(params(FastLoadByte)) require(params(FastLoadWord))
}
abstract trait RocketCoreParameters extends CoreParameters
{
require(params(RetireWidth) == 1) // for now... require(params(RetireWidth) == 1) // for now...
} }
abstract class CoreBundle extends Bundle with CoreParameters
abstract class CoreModule extends Module with CoreParameters abstract class CoreBundle extends Bundle with RocketCoreParameters
abstract class CoreModule extends Module with RocketCoreParameters
class RocketIO extends Bundle class RocketIO extends Bundle
{ {