riscv/rocket-chip
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initialize s2_hit to solve #401

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Colin Schmidt 2016-10-17 18:33:03 -07:00 committed by Colin Schmidt
parent f069052969
commit 85f3788ab5
1 changed files with 1 additions and 1 deletions
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src/main/scala/rocket/icache.scala
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@ -129,7 +129,7 @@ class ICache(latency: Int)(implicit p: Parameters) extends CoreModule()(p) with
io.resp.bits.datablock := Mux1H(s1_tag_hit, s1_dout) io.resp.bits.datablock := Mux1H(s1_tag_hit, s1_dout)
io.resp.valid := s1_hit io.resp.valid := s1_hit
case 2 => case 2 =>
val s2_hit = RegEnable(s1_hit, !stall) val s2_hit = RegEnable(s1_hit, Bool(false), !stall)
val s2_tag_hit = RegEnable(s1_tag_hit, !stall) val s2_tag_hit = RegEnable(s1_tag_hit, !stall)
val s2_dout = RegEnable(s1_dout, !stall) val s2_dout = RegEnable(s1_dout, !stall)
io.resp.bits.datablock := Mux1H(s2_tag_hit, s2_dout) io.resp.bits.datablock := Mux1H(s2_tag_hit, s2_dout)