From 85f3788ab5bf32bf9498176aa698f461c12516f9 Mon Sep 17 00:00:00 2001 From: Colin Schmidt Date: Mon, 17 Oct 2016 18:33:03 -0700 Subject: [PATCH] initialize s2_hit to solve #401 --- src/main/scala/rocket/icache.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/rocket/icache.scala b/src/main/scala/rocket/icache.scala index 4f40228a..ef90453e 100644 --- a/src/main/scala/rocket/icache.scala +++ b/src/main/scala/rocket/icache.scala @@ -129,7 +129,7 @@ class ICache(latency: Int)(implicit p: Parameters) extends CoreModule()(p) with io.resp.bits.datablock := Mux1H(s1_tag_hit, s1_dout) io.resp.valid := s1_hit case 2 => - val s2_hit = RegEnable(s1_hit, !stall) + val s2_hit = RegEnable(s1_hit, Bool(false), !stall) val s2_tag_hit = RegEnable(s1_tag_hit, !stall) val s2_dout = RegEnable(s1_dout, !stall) io.resp.bits.datablock := Mux1H(s2_tag_hit, s2_dout)