riscv/rocket-chip
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remove redundant verilator rule

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Howard Mao 2016-09-14 20:29:55 -07:00
parent a304695ffd
commit 8550582f84
1 changed files with 1 additions and 2 deletions
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vsim/Makefrag-verilog
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@ -6,9 +6,8 @@
.SECONDARY: $(generated_dir)/$(MODEL).$(CONFIG).fir .SECONDARY: $(generated_dir)/$(MODEL).$(CONFIG).fir
firrtl: $(generated_dir)/$(MODEL).$(CONFIG).fir firrtl: $(generated_dir)/$(MODEL).$(CONFIG).fir
verilog: $(generated_dir)/$(MODEL).$(CONFIG).v
.PHONY: firrtl verilog .PHONY: firrtl
$(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).d $(generated_dir)/%.prm: $(chisel_srcs) $(bootrom_img) $(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).d $(generated_dir)/%.prm: $(chisel_srcs) $(bootrom_img)
mkdir -p $(dir $@) mkdir -p $(dir $@)