From 8550582f8435c03fb6fadcc4855b15eed3c02b87 Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Wed, 14 Sep 2016 20:29:55 -0700
Subject: [PATCH] remove redundant verilator rule

---
 vsim/Makefrag-verilog | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/vsim/Makefrag-verilog b/vsim/Makefrag-verilog
index d8a3f062..00785e33 100644
--- a/vsim/Makefrag-verilog
+++ b/vsim/Makefrag-verilog
@@ -6,9 +6,8 @@
 .SECONDARY: $(generated_dir)/$(MODEL).$(CONFIG).fir
 
 firrtl: $(generated_dir)/$(MODEL).$(CONFIG).fir
-verilog: $(generated_dir)/$(MODEL).$(CONFIG).v
 
-.PHONY: firrtl verilog
+.PHONY: firrtl
 
 $(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).d $(generated_dir)/%.prm: $(chisel_srcs) $(bootrom_img)
 	mkdir -p $(dir $@)