riscv/rocket-chip
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coreplex => subsystem

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This commit is contained in:
Henry Cook
2018-01-12 12:29:27 -08:00
parent 32c5c3c04d
commit 8462ea3d5b
45 changed files with 114 additions and 114 deletions
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4
src/main/scala/tile/RocketTile.scala
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@ -5,7 +5,7 @@ package freechips.rocketchip.tile
import Chisel._
import freechips.rocketchip.config._
import freechips.rocketchip.coreplex.CoreplexClockCrossing
import freechips.rocketchip.subsystem.SubsystemClockCrossing
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.interrupts._
@ -33,7 +33,7 @@ case class RocketTileParams(
class RocketTile(
val rocketParams: RocketTileParams,
crossing: CoreplexClockCrossing)
crossing: SubsystemClockCrossing)
(implicit p: Parameters) extends BaseTile(rocketParams, crossing)(p)
with HasExternalInterrupts
with HasLazyRoCC // implies CanHaveSharedFPU with CanHavePTW with HasHellaCache