riscv/rocket-chip
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coreplex => subsystem

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This commit is contained in:
Henry Cook
2018-01-12 12:29:27 -08:00
parent 32c5c3c04d
commit 8462ea3d5b
45 changed files with 114 additions and 114 deletions
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4
src/main/scala/tile/BaseTile.scala
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@ -5,7 +5,7 @@ package freechips.rocketchip.tile
import Chisel._
import freechips.rocketchip.config._
import freechips.rocketchip.coreplex._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.interrupts._
import freechips.rocketchip.rocket._
@ -122,7 +122,7 @@ trait HasTileParameters {
}
/** Base class for all Tiles that use TileLink */
abstract class BaseTile(tileParams: TileParams, val crossing: CoreplexClockCrossing)
abstract class BaseTile(tileParams: TileParams, val crossing: SubsystemClockCrossing)
(implicit p: Parameters) extends LazyModule with HasTileParameters with HasCrossing
{
def module: BaseTileModuleImp[BaseTile]