riscv/rocket-chip
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coreplex => subsystem

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This commit is contained in:
Henry Cook
2018-01-12 12:29:27 -08:00
parent 32c5c3c04d
commit 8462ea3d5b
45 changed files with 114 additions and 114 deletions
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6
src/main/scala/system/Configs.scala
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@ -5,13 +5,13 @@ package freechips.rocketchip.system
import Chisel._
import freechips.rocketchip.config.Config
import freechips.rocketchip.coreplex._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.devices.debug.{IncludeJtagDTM, JtagDTMKey}
import freechips.rocketchip.diplomacy._
class WithJtagDTMSystem extends freechips.rocketchip.coreplex.WithJtagDTM
class WithJtagDTMSystem extends freechips.rocketchip.subsystem.WithJtagDTM
class BaseConfig extends Config(new BaseCoreplexConfig().alter((site,here,up) => {
class BaseConfig extends Config(new BaseSubsystemConfig().alter((site,here,up) => {
// DTS descriptive parameters
case DTSModel => "freechips,rocketchip-unknown"
case DTSCompat => Nil

8
src/main/scala/system/ExampleRocketSystem.scala
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@ -4,12 +4,12 @@ package freechips.rocketchip.system
import Chisel._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.coreplex._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.util.DontTouch
/** Example Top with periphery devices and ports, and a Rocket coreplex */
class ExampleRocketSystem(implicit p: Parameters) extends RocketCoreplex
/** Example Top with periphery devices and ports, and a Rocket subsystem */
class ExampleRocketSystem(implicit p: Parameters) extends RocketSubsystem
with HasAsyncExtInterrupts
with HasMasterAXI4MemPort
with HasMasterAXI4MMIOPort
@ -19,7 +19,7 @@ class ExampleRocketSystem(implicit p: Parameters) extends RocketCoreplex
override lazy val module = new ExampleRocketSystemModule(this)
}
class ExampleRocketSystemModule[+L <: ExampleRocketSystem](_outer: L) extends RocketCoreplexModule(_outer)
class ExampleRocketSystemModule[+L <: ExampleRocketSystem](_outer: L) extends RocketSubsystemModule(_outer)
with HasRTCModuleImp
with HasExtInterruptsModuleImp
with HasMasterAXI4MemPortModuleImp

6
src/main/scala/system/Generator.scala
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@ -2,13 +2,13 @@
package freechips.rocketchip.system
import freechips.rocketchip.coreplex.RocketTilesKey
import freechips.rocketchip.subsystem.RocketTilesKey
import freechips.rocketchip.tile.XLen
import freechips.rocketchip.util.GeneratorApp
import scala.collection.mutable.LinkedHashSet
/** A Generator for platforms containing Rocket Coreplexes */
/** A Generator for platforms containing Rocket Subsystemes */
object Generator extends GeneratorApp {
val rv64RegrTestNames = LinkedHashSet(
@ -50,7 +50,7 @@ object Generator extends GeneratorApp {
override def addTestSuites {
import DefaultTestSuites._
val xlen = params(XLen)
// TODO: for now only generate tests for the first core in the first coreplex
// TODO: for now only generate tests for the first core in the first subsystem
val tileParams = params(RocketTilesKey).head
val coreParams = tileParams.core
val vm = coreParams.useVM