riscv/rocket-chip
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coreplex => subsystem

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Henry Cook committed 2018-02-21 14:42:24 -08:00
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commit 8462ea3d5b
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+114 -114
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src/main/scala/rocket/Frontend.scala
+1 -1
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@@ -7,7 +7,7 @@ import Chisel._
import Chisel.ImplicitConversions._
import chisel3.core.withReset
import freechips.rocketchip.config._
import freechips.rocketchip.coreplex._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.tile._