riscv/rocket-chip
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coreplex => subsystem

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This commit is contained in:
Henry Cook
2018-01-12 12:29:27 -08:00
parent 32c5c3c04d
commit 8462ea3d5b
45 changed files with 114 additions and 114 deletions
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4
src/main/scala/devices/tilelink/Plic.scala
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@ -5,7 +5,7 @@ package freechips.rocketchip.devices.tilelink
import Chisel._
import Chisel.ImplicitConversions._
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.coreplex.{HasInterruptBus, HasPeripheryBus}
import freechips.rocketchip.subsystem.{HasInterruptBus, HasPeripheryBus}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._
@ -268,7 +268,7 @@ class TLPLIC(params: PLICParams, beatBytes: Int)(implicit p: Parameters) extends
}
}
/** Trait that will connect a PLIC to a coreplex */
/** Trait that will connect a PLIC to a subsystem */
trait HasPeripheryPLIC extends HasInterruptBus with HasPeripheryBus {
val plic = LazyModule(new TLPLIC(p(PLICKey), pbus.beatBytes))
plic.node := pbus.toVariableWidthSlaves