riscv/rocket-chip
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coreplex => subsystem

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Henry Cook committed 2018-02-21 14:42:24 -08:00
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commit 8462ea3d5b
45 files changed
+114 -114
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src/main/scala/devices/debug/Periphery.scala
+1 -1
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@@ -5,7 +5,7 @@ package freechips.rocketchip.devices.debug
import Chisel._
import chisel3.core.{IntParam, Input, Output}
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.coreplex.HasPeripheryBus
import freechips.rocketchip.subsystem.HasPeripheryBus
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.jtag._