riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

coreplex: fix TinyConfig

Browse Source
This commit is contained in:
Wesley W. Terpstra 2016-10-28 21:34:04 -07:00
parent ba529c3716
commit 841a31479a
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/coreplex/BaseCoreplex.scala
View File

@ -53,7 +53,7 @@ trait CoreplexNetwork extends HasCoreplexParameters {
this: BareCoreplex =>
val l1tol2 = LazyModule(new TLXbar)
val l1tol2_beatBytes = p(rocketchip.EdgeDataBits)/8
val l1tol2_beatBytes = p(TLKey("L2toMMIO")).dataBitsPerBeat/8
val l1tol2_lineBytes = p(CacheBlockBytes)
val cbus = LazyModule(new TLXbar)