From 841a31479a15e2603444b97be3c7d23089e8e415 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Fri, 28 Oct 2016 21:34:04 -0700 Subject: [PATCH] coreplex: fix TinyConfig --- src/main/scala/coreplex/BaseCoreplex.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/coreplex/BaseCoreplex.scala b/src/main/scala/coreplex/BaseCoreplex.scala index 52482d1f..63cbec7a 100644 --- a/src/main/scala/coreplex/BaseCoreplex.scala +++ b/src/main/scala/coreplex/BaseCoreplex.scala @@ -53,7 +53,7 @@ trait CoreplexNetwork extends HasCoreplexParameters { this: BareCoreplex => val l1tol2 = LazyModule(new TLXbar) - val l1tol2_beatBytes = p(rocketchip.EdgeDataBits)/8 + val l1tol2_beatBytes = p(TLKey("L2toMMIO")).dataBitsPerBeat/8 val l1tol2_lineBytes = p(CacheBlockBytes) val cbus = LazyModule(new TLXbar)