riscv/rocket-chip
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coreplex: fix TinyConfig

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This commit is contained in:
Wesley W. Terpstra 2016-10-28 21:34:04 -07:00
parent ba529c3716
commit 841a31479a
1 changed files with 1 additions and 1 deletions
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src/main/scala/coreplex/BaseCoreplex.scala
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@ -53,7 +53,7 @@ trait CoreplexNetwork extends HasCoreplexParameters {
this: BareCoreplex => this: BareCoreplex =>
val l1tol2 = LazyModule(new TLXbar) val l1tol2 = LazyModule(new TLXbar)
val l1tol2_beatBytes = p(rocketchip.EdgeDataBits)/8 val l1tol2_beatBytes = p(TLKey("L2toMMIO")).dataBitsPerBeat/8
val l1tol2_lineBytes = p(CacheBlockBytes) val l1tol2_lineBytes = p(CacheBlockBytes)
val cbus = LazyModule(new TLXbar) val cbus = LazyModule(new TLXbar)