riscv/rocket-chip
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Bypass TLB refill signal to halve L2 TLB hit time

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The 4-cycle hit time is 1 cycle too long to avoid a second
pipeline replay, so it was effectively 9 cycles instead of 4.
This commit is contained in:
Andrew Waterman 2017-07-26 16:55:45 -07:00
parent ae1f7a95f6
commit 838864870e
1 changed files with 1 additions and 1 deletions
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src/main/scala/rocket/DCache.scala
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@ -153,7 +153,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
tlb.io.req.bits.instruction := false tlb.io.req.bits.instruction := false
tlb.io.req.bits.size := s1_req.typ tlb.io.req.bits.size := s1_req.typ
tlb.io.req.bits.cmd := s1_req.cmd tlb.io.req.bits.cmd := s1_req.cmd
when (!tlb.io.req.ready && !io.cpu.req.bits.phys) { io.cpu.req.ready := false } when (!tlb.io.req.ready && !tlb.io.ptw.resp.valid && !io.cpu.req.bits.phys) { io.cpu.req.ready := false }
when (s1_valid && s1_readwrite && tlb.io.resp.miss) { s1_nack := true } when (s1_valid && s1_readwrite && tlb.io.resp.miss) { s1_nack := true }
val s1_paddr = tlb.io.resp.paddr val s1_paddr = tlb.io.resp.paddr