From 838864870ebd6551f1d2c9ca7f05bf4e075f28ef Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 26 Jul 2017 16:55:45 -0700 Subject: [PATCH] Bypass TLB refill signal to halve L2 TLB hit time The 4-cycle hit time is 1 cycle too long to avoid a second pipeline replay, so it was effectively 9 cycles instead of 4. --- src/main/scala/rocket/DCache.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala index 204725b2..59007622 100644 --- a/src/main/scala/rocket/DCache.scala +++ b/src/main/scala/rocket/DCache.scala @@ -153,7 +153,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { tlb.io.req.bits.instruction := false tlb.io.req.bits.size := s1_req.typ tlb.io.req.bits.cmd := s1_req.cmd - when (!tlb.io.req.ready && !io.cpu.req.bits.phys) { io.cpu.req.ready := false } + when (!tlb.io.req.ready && !tlb.io.ptw.resp.valid && !io.cpu.req.bits.phys) { io.cpu.req.ready := false } when (s1_valid && s1_readwrite && tlb.io.resp.miss) { s1_nack := true } val s1_paddr = tlb.io.resp.paddr