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add a debug print for xbar id mappings

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Colin Schmidt 2017-06-13 14:32:35 -07:00 committed by Wesley W. Terpstra
parent 8278d22fcd
commit 8264c0a77e
1 changed files with 10 additions and 1 deletions
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11
src/main/scala/uncore/tilelink2/Xbar.scala
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@ -84,7 +84,7 @@ class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Parame
val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct)) val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct))
val outputPorts = route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _)) val outputPorts = route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _))
// Print the mapping // Print the address mapping
if (false) { if (false) {
println("Xbar mapping:") println("Xbar mapping:")
route_addrs.foreach { p => route_addrs.foreach { p =>
@ -95,6 +95,15 @@ class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Parame
println("--") println("--")
} }
// Print the ID mapping
if (false) {
println(s"XBar ${name} mapping:")
(node.edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) =>
println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}")
}
println("")
}
// We need an intermediate size of bundle with the widest possible identifiers // We need an intermediate size of bundle with the widest possible identifiers
val wide_bundle = io.in(0).params.union(io.out(0).params) val wide_bundle = io.in(0).params.union(io.out(0).params)