diff --git a/src/main/scala/uncore/tilelink2/Xbar.scala b/src/main/scala/uncore/tilelink2/Xbar.scala
index b4eef8dc..b331fcad 100644
--- a/src/main/scala/uncore/tilelink2/Xbar.scala
+++ b/src/main/scala/uncore/tilelink2/Xbar.scala
@@ -84,7 +84,7 @@ class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Parame
     val route_addrs = port_addrs.map(seq => AddressSet.unify(seq.map(_.widen(~routingMask)).distinct))
     val outputPorts = route_addrs.map(seq => (addr: UInt) => seq.map(_.contains(addr)).reduce(_ || _))
 
-    // Print the mapping
+    // Print the address mapping
     if (false) {
       println("Xbar mapping:")
       route_addrs.foreach { p =>
@@ -95,6 +95,15 @@ class TLXbar(policy: TLArbiter.Policy = TLArbiter.roundRobin)(implicit p: Parame
       println("--")
     }
 
+    // Print the ID mapping
+    if (false) {
+      println(s"XBar ${name} mapping:")
+      (node.edgesIn zip inputIdRanges).zipWithIndex.foreach { case ((edge, id), i) =>
+        println(s"\t$i assigned ${id} for ${edge.client.clients.map(_.name).mkString(", ")}")
+      }
+      println("")
+    }
+
     // We need an intermediate size of bundle with the widest possible identifiers
     val wide_bundle = io.in(0).params.union(io.out(0).params)