merge in rocketchip changes from master

src/main/scala/Backends.scala

@@ -1,14 +1,14 @@
-package referencechip
+package rocketchip
 
 import Chisel._
-import ReferenceChipBackend._
+import RocketChipBackend._
 import scala.collection.mutable.HashMap
 
-object ReferenceChipBackend {
+object RocketChipBackend {
   val initMap = new HashMap[Module, Bool]()
 }
 
-class ReferenceChipBackend extends VerilogBackend
+class RocketChipBackend extends VerilogBackend
 {
   initMap.clear()
   override def emitPortDef(m: MemAccess, idx: Int) = {
@@ -65,5 +65,5 @@ class ReferenceChipBackend extends VerilogBackend
   transforms += ((c: Module) => collectNodesIntoComp(initializeDFS))
 }
 
-class Fame1ReferenceChipBackend extends ReferenceChipBackend with Fame1Transform
+class Fame1RocketChipBackend extends RocketChipBackend with Fame1Transform
 

src/main/scala/PublicConfigs.scala

@@ -1,4 +1,4 @@
-package referencechip
+package rocketchip
 
 import Chisel._
 import uncore._

src/main/scala/RocketChip.scala

@@ -1,4 +1,4 @@
-package referencechip
+package rocketchip
 
 import Chisel._
 import uncore._
@@ -33,7 +33,7 @@ class OuterMemorySystem extends Module with TopLevelParameters {
   }
 
   // Create a simple NoC and points of coherence serialization
-  val net = Module(new ReferenceChipCrossbarNetwork)
+  val net = Module(new RocketChipCrossbarNetwork)
   val masterEndpoints = (0 until params(NBanks)).map(params(BuildCoherenceMaster))
   net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end }
   net.io.masters zip (masterEndpoints.map(_.io.inner)) map { case (net, end) => net <> end }

src/main/scala/fpga.scala

@@ -1,18 +1,7 @@
-package referencechip
+package rocketchip
 
 import Chisel._
 
-  /*
-  val ntiles = 1
-  val nmshrs = 2
-  implicit val uc = FPGAUncoreConfiguration(l2, tl, mif, ntiles, nSCR = 64, offsetBits = params[Int]("OFFSET_BITS"))
-
-  val ic = ICacheConfig(64, 1, ntlb = 4, tl = tl, as = as, btb = BTBConfig(as, 8, 2))
-  val dc = DCacheConfig(64, 1, ntlb = 4, nmshr = 2, nrpq = 16, nsdq = 17, tl = tl, as = as, reqtagbits = -1, databits = -1)
-  val rc = RocketConfiguration(tl, as, ic, dc,
-                               fastMulDiv = false)
-*/
-
 abstract class AXISlave extends Module {
   val aw = 5
   val dw = 32

src/main/scala/network.scala

@@ -1,4 +1,4 @@
-package referencechip
+package rocketchip
 
 import Chisel._
 import uncore._
@@ -22,7 +22,7 @@ object TileLinkHeaderOverwriter {
   }
 }
 
-class ReferenceChipCrossbarNetwork extends LogicalNetwork {
+class RocketChipCrossbarNetwork extends LogicalNetwork {
   val io = new Bundle {
     val clients = Vec.fill(params(LNClients)){(new TileLinkIO).flip}
     val masters = Vec.fill(params(LNMasters)){new TileLinkIO}

src/main/scala/vlsi.scala

@@ -1,4 +1,4 @@
-package referencechip
+package rocketchip
 
 import Chisel._
 import uncore._