riscv/rocket-chip
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Dynamically compute number of L1 client channels

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Until now, the number of L1 client channels was set statically in the
configuration. This static configuration also assumed the same number of
cached and uncached channels per tile. As we plan to move towards
heterogenous multicore systems, this restriction should be removed.

This commit changes the generator so that number of channels per tile
can be independently set (using cde.Parameters.alterPartial).
The OuterMemorySystem will dynamically compute the number of cached and
uncached channels by summing the number of each kind of channel per core.
This commit is contained in:
Howard Mao
2016-06-13 16:24:01 -07:00
parent 4a8e6c773a
commit 82169e971e
9 changed files with 155 additions and 87 deletions
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34
src/main/scala/RocketChip.scala
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@ -39,8 +39,6 @@ case object BuildL2CoherenceManager extends Field[(Int, Parameters) => Coherence
case object BuildTiles extends Field[Seq[(Bool, Parameters) => Tile]]
/** A string describing on-chip devices, readable by target software */
case object ConfigString extends Field[Array[Byte]]
/** Number of L1 clients besides the CPU cores */
case object ExtraL1Clients extends Field[Int]
/** Number of external interrupt sources */
case object NExtInterrupts extends Field[Int]
/** Interrupt controller configuration */
@ -54,9 +52,8 @@ case object StreamLoopbackWidth extends Field[Int]
trait HasTopLevelParameters {
implicit val p: Parameters
lazy val nTiles = p(NTiles)
lazy val nCachedTilePorts = p(TLKey("L1toL2")).nCachingClients
lazy val nUncachedTilePorts =
p(TLKey("L1toL2")).nCachelessClients - p(ExtraL1Clients)
lazy val nCachedTilePorts = p(NCachedTileLinkPorts)
lazy val nUncachedTilePorts = p(NUncachedTileLinkPorts) - 1
lazy val htifW = p(HtifKey).width
lazy val csrAddrBits = 12
lazy val tMemChannels = p(TMemoryChannels)
@ -143,13 +140,26 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
val io = new TopIO
// Build an Uncore and a set of Tiles
val innerTLParams = p.alterPartial({case HastiId => "TL" case TLId => "L1toL2" })
val uncore = Module(new Uncore()(innerTLParams))
val tileList = uncore.io.prci zip p(BuildTiles) map { case(prci, tile) => tile(prci.reset, p) }
val tileResets = Wire(Vec(nTiles, Bool()))
val tileList = p(BuildTiles).zip(tileResets).map {
case (tile, rst) => tile(rst, p)
}
val nCachedPorts = tileList.map(tile => tile.io.cached.size).reduce(_ + _)
val nUncachedPorts = tileList.map(tile => tile.io.uncached.size).reduce(_ + _)
// Connect each tile to the HTIF
for ((prci, tile) <- uncore.io.prci zip tileList) {
tile.io.prci <> prci
val innerTLParams = p.alterPartial({
case HastiId => "TL"
case TLId => "L1toL2"
case NCachedTileLinkPorts => nCachedPorts
case NUncachedTileLinkPorts => nUncachedPorts + 1 // 1 for HTIF
})
val uncore = Module(new Uncore()(innerTLParams))
uncore.io.prci.zip(tileResets).zip(tileList).foreach {
case ((prci, rst), tile) =>
rst := prci.reset
tile.io.prci <> prci
}
// Connect the uncore to the tile memory ports, HostIO and MemIO
@ -172,6 +182,8 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
*/
class Uncore(implicit val p: Parameters) extends Module
with HasTopLevelParameters {
val io = new Bundle {
val host = new HostIO(htifW)
val mem_axi = Vec(nMemAXIChannels, new NastiIO)