diff --git a/.travis.yml b/.travis.yml
index 2744f302..f47e6f17 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -43,6 +43,8 @@ env:
     - CONFIG=NastiConverterTestConfig       CHISEL_VERSION=3
     - CONFIG=UnitTestConfig                 CHISEL_VERSION=3
     - CONFIG=SplitL2MetadataTestConfig      CHISEL_VERSION=3
+    - CONFIG=ComparatorConfig               CHISEL_VERSION=3
+    - CONFIG=ComparatorL2Config             CHISEL_VERSION=3
 
 # blacklist private branches
 branches:
diff --git a/groundtest b/groundtest
index 97ef13b5..11898a03 160000
--- a/groundtest
+++ b/groundtest
@@ -1 +1 @@
-Subproject commit 97ef13b5edfdd7b2f3c5ccd64eb7497807a29c8c
+Subproject commit 11898a03c43aac88ced69c539f8dc04bfebd7ccf
diff --git a/junctions b/junctions
index f9dda560..d39a2045 160000
--- a/junctions
+++ b/junctions
@@ -1 +1 @@
-Subproject commit f9dda56073a68c2dccd10fbbbb84b9903cf093da
+Subproject commit d39a2045c6ab975f8ae52d08861f19573400bd2a
diff --git a/rocket b/rocket
index 94096e83..b029249c 160000
--- a/rocket
+++ b/rocket
@@ -1 +1 @@
-Subproject commit 94096e83ed58f2afaacdeb99ed2d885e3589d3f6
+Subproject commit b029249ccb8c3f57b2a6720e2091e09dafc8365c
diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala
index d7402e28..236e854f 100644
--- a/src/main/scala/Configs.scala
+++ b/src/main/scala/Configs.scala
@@ -178,6 +178,8 @@ class BaseConfig extends Config (
         Module(new L2BroadcastHub()(p.alterPartial({
           case InnerTLId => "L1toL2"
           case OuterTLId => "L2toMC" })))
+      case NCachedTileLinkPorts => 1
+      case NUncachedTileLinkPorts => 1
       //Tile Constants
       case BuildTiles => {
         val (rvi, rvu) =
@@ -187,7 +189,10 @@ class BaseConfig extends Config (
         TestGeneration.addSuites((if(site(UseVM)) List("v") else List()).flatMap(env => rvu.map(_(env))))
         TestGeneration.addSuite(bmarks)
         List.fill(site(NTiles)){ (r: Bool, p: Parameters) =>
-          Module(new RocketTile(resetSignal = r)(p.alterPartial({case TLId => "L1toL2"})))
+          Module(new RocketTile(resetSignal = r)(p.alterPartial({
+            case TLId => "L1toL2"
+            case NUncachedTileLinkPorts => 1 + site(RoccNMemChannels)
+          })))
         }
       }
       case BuildRoCC => Nil
@@ -239,7 +244,6 @@ class BaseConfig extends Config (
       case LNEndpoints => site(TLKey(site(TLId))).nManagers + site(TLKey(site(TLId))).nClients
       case LNHeaderBits => log2Ceil(site(TLKey(site(TLId))).nManagers) +
                              log2Up(site(TLKey(site(TLId))).nClients)
-      case ExtraL1Clients => 1 // HTIF // TODO not really a parameter
       case HastiId => "Ext"
       case HastiKey("TL") =>
         HastiParameters(
@@ -253,11 +257,8 @@ class BaseConfig extends Config (
         TileLinkParameters(
           coherencePolicy = new MESICoherence(site(L2DirectoryRepresentation)),
           nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1,
-          nCachingClients = site(NTiles),
-          nCachelessClients = site(ExtraL1Clients) +
-                              site(NTiles) *
-                                (1 + (if(site(BuildRoCC).isEmpty) 0
-                                      else site(RoccNMemChannels))),
+          nCachingClients = site(NCachedTileLinkPorts),
+          nCachelessClients = site(NUncachedTileLinkPorts),
           maxClientXacts = max_int(
               // L1 cache
               site(NMSHRs) + 1,
@@ -324,29 +325,18 @@ class BaseConfig extends Config (
 )
 class DefaultConfig extends Config(new WithBlockingL1 ++ new BaseConfig)
 
-class With2Cores extends Config(knobValues = { case "NTILES" => 2; case _ => throw new CDEMatchError })
-class With4Cores extends Config(knobValues = { case "NTILES" => 4; case _ => throw new CDEMatchError })
-class With8Cores extends Config(knobValues = { case "NTILES" => 8; case _ => throw new CDEMatchError })
+class WithNCores(n: Int) extends Config(
+  knobValues = { case"NTILES" => n; case _ => throw new CDEMatchError })
 
-class With2BanksPerMemChannel extends Config(knobValues = { case "NBANKS_PER_MEM_CHANNEL" => 2; case _ => throw new CDEMatchError })
-class With4BanksPerMemChannel extends Config(knobValues = { case "NBANKS_PER_MEM_CHANNEL" => 4; case _ => throw new CDEMatchError })
-class With8BanksPerMemChannel extends Config(knobValues = { case "NBANKS_PER_MEM_CHANNEL" => 8; case _ => throw new CDEMatchError })
+class WithNBanksPerMemChannel(n: Int) extends Config(
+  knobValues = {
+    case "NBANKS_PER_MEM_CHANNEL" => n;
+    case _ => throw new CDEMatchError
+  })
 
-class With2MemoryChannels extends Config(
+class WithNMemoryChannels(n: Int) extends Config(
   (pname,site,here) => pname match {
-    case NMemoryChannels => Dump("N_MEM_CHANNELS", 2)
-    case _ => throw new CDEMatchError
-  }
-)
-class With4MemoryChannels extends Config(
-  (pname,site,here) => pname match {
-    case NMemoryChannels => Dump("N_MEM_CHANNELS", 4)
-    case _ => throw new CDEMatchError
-  }
-)
-class With8MemoryChannels extends Config(
-  (pname,site,here) => pname match {
-    case NMemoryChannels => Dump("N_MEM_CHANNELS", 8)
+    case NMemoryChannels => Dump("N_MEM_CHANNELS", n)
     case _ => throw new CDEMatchError
   }
 )
@@ -385,19 +375,21 @@ class WithPLRU extends Config(
     case _ => throw new CDEMatchError
   })
 
-class WithL2Capacity2048 extends Config(knobValues = { case "L2_CAPACITY_IN_KB" => 2048; case _ => throw new CDEMatchError })
-class WithL2Capacity1024 extends Config(knobValues = { case "L2_CAPACITY_IN_KB" => 1024; case _ => throw new CDEMatchError })
-class WithL2Capacity512 extends Config(knobValues = { case "L2_CAPACITY_IN_KB" => 512; case _ => throw new CDEMatchError })
-class WithL2Capacity256 extends Config(knobValues = { case "L2_CAPACITY_IN_KB" => 256; case _ => throw new CDEMatchError })
-class WithL2Capacity128 extends Config(knobValues = { case "L2_CAPACITY_IN_KB" => 128; case _ => throw new CDEMatchError })
-class WithL2Capacity64 extends Config(knobValues = { case "L2_CAPACITY_IN_KB" => 64; case _ => throw new CDEMatchError })
+class WithL2Capacity(size_kb: Int) extends Config(
+  knobValues = {
+    case "L2_CAPACITY_IN_KB" => size_kb
+    case _ => throw new CDEMatchError
+  })
 
-class With1L2Ways extends Config(knobValues = { case "L2_WAYS" => 1; case _ => throw new CDEMatchError })
-class With2L2Ways extends Config(knobValues = { case "L2_WAYS" => 2; case _ => throw new CDEMatchError })
-class With4L2Ways extends Config(knobValues = { case "L2_WAYS" => 4; case _ => throw new CDEMatchError })
+class WithNL2Ways(n: Int) extends Config(
+  knobValues = {
+    case "L2_WAYS" => n
+    case _ => throw new CDEMatchError
+  })
 
 class DefaultL2Config extends Config(new WithL2Cache ++ new BaseConfig)
-class DefaultL2FPGAConfig extends Config(new WithL2Capacity64 ++ new WithL2Cache ++ new DefaultFPGAConfig)
+class DefaultL2FPGAConfig extends Config(
+  new WithL2Capacity(64) ++ new WithL2Cache ++ new DefaultFPGAConfig)
 
 class PLRUL2Config extends Config(new WithPLRU ++ new DefaultL2Config)
 
@@ -462,18 +454,20 @@ class DefaultRV32Config extends Config(new SmallConfig ++ new WithRV32 ++ new Ba
 
 class ExampleSmallConfig extends Config(new SmallConfig ++ new BaseConfig)
 
-class DualBankConfig extends Config(new With2BanksPerMemChannel ++ new BaseConfig)
+class DualBankConfig extends Config(
+  new WithNBanksPerMemChannel(2) ++ new BaseConfig)
 class DualBankL2Config extends Config(
-  new With2BanksPerMemChannel ++ new WithL2Cache ++ new BaseConfig)
+  new WithNBanksPerMemChannel(2) ++ new WithL2Cache ++ new BaseConfig)
 
-class DualChannelConfig extends Config(new With2MemoryChannels ++ new BaseConfig)
+class DualChannelConfig extends Config(new WithNMemoryChannels(2) ++ new BaseConfig)
 class DualChannelL2Config extends Config(
-  new With2MemoryChannels ++ new WithL2Cache ++ new BaseConfig)
+  new WithNMemoryChannels(2) ++ new WithL2Cache ++ new BaseConfig)
 
 class DualChannelDualBankConfig extends Config(
-  new With2MemoryChannels ++ new With2BanksPerMemChannel ++ new BaseConfig)
+  new WithNMemoryChannels(2) ++
+  new WithNBanksPerMemChannel(2) ++ new BaseConfig)
 class DualChannelDualBankL2Config extends Config(
-  new With2MemoryChannels ++ new With2BanksPerMemChannel ++
+  new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(2) ++
   new WithL2Cache ++ new BaseConfig)
 
 class WithRoccExample extends Config(
@@ -522,17 +516,17 @@ class DmaControllerConfig extends Config(new WithDmaController ++ new WithStream
 class DmaControllerFPGAConfig extends Config(new WithDmaController ++ new WithStreamLoopback ++ new DefaultFPGAConfig)
 
 class SmallL2Config extends Config(
-  new With2MemoryChannels ++ new With4BanksPerMemChannel ++
-  new WithL2Capacity256 ++ new DefaultL2Config)
+  new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(4) ++
+  new WithL2Capacity(256) ++ new DefaultL2Config)
 
-class SingleChannelBenchmarkConfig extends Config(new WithL2Capacity256 ++ new DefaultL2Config)
-class DualChannelBenchmarkConfig extends Config(new With2MemoryChannels ++ new SingleChannelBenchmarkConfig)
-class QuadChannelBenchmarkConfig extends Config(new With4MemoryChannels ++ new SingleChannelBenchmarkConfig)
-class OctoChannelBenchmarkConfig extends Config(new With8MemoryChannels ++ new SingleChannelBenchmarkConfig)
+class SingleChannelBenchmarkConfig extends Config(new WithL2Capacity(256) ++ new DefaultL2Config)
+class DualChannelBenchmarkConfig extends Config(new WithNMemoryChannels(2) ++ new SingleChannelBenchmarkConfig)
+class QuadChannelBenchmarkConfig extends Config(new WithNMemoryChannels(4) ++ new SingleChannelBenchmarkConfig)
+class OctoChannelBenchmarkConfig extends Config(new WithNMemoryChannels(8) ++ new SingleChannelBenchmarkConfig)
 
-class EightChannelConfig extends Config(new With8MemoryChannels ++ new BaseConfig)
+class EightChannelConfig extends Config(new WithNMemoryChannels(8) ++ new BaseConfig)
 
 class WithSplitL2Metadata extends Config(knobValues = { case "L2_SPLIT_METADATA" => true; case _ => throw new CDEMatchError })
 class SplitL2MetadataTestConfig extends Config(new WithSplitL2Metadata ++ new DefaultL2Config)
 
-class DualCoreConfig extends Config(new With2Cores ++ new BaseConfig)
+class DualCoreConfig extends Config(new WithNCores(2) ++ new BaseConfig)
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index 55a985d3..857db3d0 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -39,8 +39,6 @@ case object BuildL2CoherenceManager extends Field[(Int, Parameters) => Coherence
 case object BuildTiles extends Field[Seq[(Bool, Parameters) => Tile]]
 /** A string describing on-chip devices, readable by target software */
 case object ConfigString extends Field[Array[Byte]]
-/** Number of L1 clients besides the CPU cores */
-case object ExtraL1Clients extends Field[Int] 
 /** Number of external interrupt sources */
 case object NExtInterrupts extends Field[Int]
 /** Interrupt controller configuration */
@@ -54,9 +52,8 @@ case object StreamLoopbackWidth extends Field[Int]
 trait HasTopLevelParameters {
   implicit val p: Parameters
   lazy val nTiles = p(NTiles)
-  lazy val nCachedTilePorts = p(TLKey("L1toL2")).nCachingClients
-  lazy val nUncachedTilePorts =
-    p(TLKey("L1toL2")).nCachelessClients - p(ExtraL1Clients)
+  lazy val nCachedTilePorts = p(NCachedTileLinkPorts)
+  lazy val nUncachedTilePorts = p(NUncachedTileLinkPorts) - 1
   lazy val htifW = p(HtifKey).width
   lazy val csrAddrBits = 12
   lazy val tMemChannels = p(TMemoryChannels)
@@ -143,13 +140,26 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
   val io = new TopIO
 
   // Build an Uncore and a set of Tiles
-  val innerTLParams = p.alterPartial({case HastiId => "TL" case TLId => "L1toL2" })
-  val uncore = Module(new Uncore()(innerTLParams))
-  val tileList = uncore.io.prci zip p(BuildTiles) map { case(prci, tile) => tile(prci.reset, p) }
+  val tileResets = Wire(Vec(nTiles, Bool()))
+  val tileList = p(BuildTiles).zip(tileResets).map {
+    case (tile, rst) => tile(rst, p)
+  }
+  val nCachedPorts = tileList.map(tile => tile.io.cached.size).reduce(_ + _)
+  val nUncachedPorts = tileList.map(tile => tile.io.uncached.size).reduce(_ + _)
 
-  // Connect each tile to the HTIF
-  for ((prci, tile) <- uncore.io.prci zip tileList) {
-    tile.io.prci <> prci
+  val innerTLParams = p.alterPartial({
+    case HastiId => "TL"
+    case TLId => "L1toL2"
+    case NCachedTileLinkPorts => nCachedPorts
+    case NUncachedTileLinkPorts => nUncachedPorts + 1 // 1 for HTIF
+  })
+
+  val uncore = Module(new Uncore()(innerTLParams))
+
+  uncore.io.prci.zip(tileResets).zip(tileList).foreach {
+    case ((prci, rst), tile) =>
+      rst := prci.reset
+      tile.io.prci <> prci
   }
 
   // Connect the uncore to the tile memory ports, HostIO and MemIO
@@ -172,6 +182,8 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
   */
 class Uncore(implicit val p: Parameters) extends Module
     with HasTopLevelParameters {
+
+
   val io = new Bundle {
     val host = new HostIO(htifW)
     val mem_axi = Vec(nMemAXIChannels, new NastiIO)
diff --git a/src/main/scala/TestConfigs.scala b/src/main/scala/TestConfigs.scala
index d551d5ae..5f7f21cf 100644
--- a/src/main/scala/TestConfigs.scala
+++ b/src/main/scala/TestConfigs.scala
@@ -16,12 +16,12 @@ class WithGroundTest extends Config(
       TileLinkParameters(
         coherencePolicy = new MESICoherence(site(L2DirectoryRepresentation)),
         nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1,
-        nCachingClients = site(NTiles),
-        nCachelessClients = site(NTiles) + site(ExtraL1Clients),
+        nCachingClients = site(NCachedTileLinkPorts),
+        nCachelessClients = site(NUncachedTileLinkPorts),
         maxClientXacts = max(
           site(NMSHRs) + 1,
           site(GroundTestMaxXacts)),
-        maxClientsPerPort = 2,
+        maxClientsPerPort = 1,
         maxManagerXacts = site(NAcquireTransactors) + 2,
         dataBeats = site(MIFDataBeats),
         dataBits = site(CacheBlockBytes)*8)
@@ -34,16 +34,22 @@ class WithGroundTest extends Config(
       TestGeneration.addSuite(DefaultTestSuites.emptyBmarks)
       (0 until site(NTiles)).map { i =>
         (r: Bool, p: Parameters) =>
-          Module(new GroundTestTile(i, r)
-            (p.alterPartial({case TLId => "L1toL2"})))
+          Module(new GroundTestTile(i, r)(p.alterPartial({
+            case TLId => "L1toL2"
+            case NUncachedTileLinkPorts =>
+              (if (i == 0) 1 else 0) + p(GroundTestUncachedClients)
+          })))
       }
     }
+    case GroundTestCachedClients => 0
+    case GroundTestUncachedClients => 0
+    case GroundTestNPTW => 0
     case GroundTestMaxXacts => 1
     case GroundTestCSRs => Nil
     case TohostAddr => BigInt("80001000", 16)
     case RoccNCSRs => site(GroundTestCSRs).size
     case UseFPU => false
-    case UseAtomics => true
+    case UseAtomics => false
     case _ => throw new CDEMatchError
   })
 
@@ -53,32 +59,57 @@ class WithComparator extends Config(
       TileLinkParameters(
         coherencePolicy = new MESICoherence(site(L2DirectoryRepresentation)),
         nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1,
-        nCachingClients = 1,
-        nCachelessClients = 1 + site(ComparatorKey).targets.size + site(ExtraL1Clients),
+        nCachingClients = site(NCachedTileLinkPorts),
+        nCachelessClients = site(NUncachedTileLinkPorts),
         maxClientXacts = 2,
         maxClientsPerPort = 1,
         maxManagerXacts = site(NAcquireTransactors) + 2,
         dataBeats = site(MIFDataBeats),
         dataBits = site(CacheBlockBytes)*8)
-    case BuildTiles =>
-      Seq((r: Bool, p: Parameters) => Module(new ComparatorTile(r)(p.alterPartial({case TLId => "L1toL2"}))))
+    case BuildTiles => {
+      val groundtest = if (site(XLen) == 64)
+        DefaultTestSuites.groundtest64
+      else
+        DefaultTestSuites.groundtest32
+      TestGeneration.addSuite(groundtest("p"))
+      TestGeneration.addSuite(DefaultTestSuites.emptyBmarks)
+      Seq((r: Bool, p: Parameters) => Module(new ComparatorTile(r)(
+        p.alterPartial({
+          case TLId => "L1toL2"
+          case NUncachedTileLinkPorts => 1 + site(ComparatorKey).targets.size
+        }))))
+    }
     case ComparatorKey => ComparatorParameters(
-      targets    = Seq(0x80001000L, 0x80000000L),
+      targets    = Seq(0L, 0x100L).map(site(GlobalAddrMap)("mem").start.longValue + _),
       width      = 8,
       operations = 1000,
-      atomics    = true)
-    case RoccNMemChannels => site(ComparatorKey).targets.size // Work-around bad rocket<>tile dependency
+      atomics    = site(UseAtomics),
+      prefetches = site("COMPARATOR_PREFETCHES"))
+    case NUncachedTileLinkPorts => 1 + site(ComparatorKey).targets.size
     case TohostAddr => BigInt("80001000", 16) // quit test by writing here
+    case UseFPU => false
+    case UseAtomics => false
+    case "COMPARATOR_PREFETCHES" => false
     case _ => throw new CDEMatchError
   })
 
+class WithAtomics extends Config(
+  (pname, site, here) => pname match {
+    case UseAtomics => true
+  })
+
+class WithPrefetches extends Config(
+  (pname, site, here) => pname match {
+    case "COMPARATOR_PREFETCHES" => true
+  })
+
 class WithMemtest extends Config(
   (pname, site, here) => pname match {
-    case NGenerators => site(NTiles)
-    case GenerateUncached => true
-    case GenerateCached => true
+    case GroundTestCachedClients => 1
+    case GroundTestUncachedClients => 1
+    case GroundTestNPTW => 0
     case MaxGenerateRequests => 128
-    case GeneratorStartAddress => site(GlobalAddrMap)("mem").start
+    case GeneratorStartAddress => site(TohostAddr) + BigInt(site(CacheBlockBytes))
     case BuildGroundTest =>
       (id: Int, p: Parameters) => Module(new GeneratorTest(id)(p))
     case _ => throw new CDEMatchError
@@ -86,6 +117,7 @@ class WithMemtest extends Config(
 
 class WithCacheFillTest extends Config(
   (pname, site, here) => pname match {
+    case GroundTestUncachedClients => 1
     case BuildGroundTest =>
       (id: Int, p: Parameters) => Module(new CacheFillTest()(p))
     case _ => throw new CDEMatchError
@@ -98,6 +130,8 @@ class WithCacheFillTest extends Config(
 
 class WithBroadcastRegressionTest extends Config(
   (pname, site, here) => pname match {
+    case GroundTestCachedClients => 1
+    case GroundTestUncachedClients => 1
     case BuildGroundTest =>
       (id: Int, p: Parameters) => Module(new RegressionTest()(p))
     case GroundTestRegressions =>
@@ -108,16 +142,20 @@ class WithBroadcastRegressionTest extends Config(
 
 class WithCacheRegressionTest extends Config(
   (pname, site, here) => pname match {
+    case GroundTestCachedClients => 1
+    case GroundTestUncachedClients => 1
     case BuildGroundTest =>
       (id: Int, p: Parameters) => Module(new RegressionTest()(p))
     case GroundTestRegressions =>
       (p: Parameters) => RegressionTests.cacheRegressions(p)
-    case GroundTestMaxXacts => 3
+    case GroundTestMaxXacts => 5
     case _ => throw new CDEMatchError
   })
 
 class WithDmaTest extends Config(
   (pname, site, here) => pname match {
+    case GroundTestNPTW => 1
+    case GroundTestUncachedClients => 1
     case BuildGroundTest =>
       (id: Int, p: Parameters) => Module(new DmaTest()(p))
     case DmaTestSet => DmaTestCases(
@@ -134,6 +172,8 @@ class WithDmaTest extends Config(
 
 class WithDmaStreamTest extends Config(
   (pname, site, here) => pname match {
+    case GroundTestNPTW => 1
+    case GroundTestUncachedClients => 1
     case BuildGroundTest =>
       (id: Int, p: Parameters) => Module(new DmaStreamTest()(p))
     case DmaStreamTestSettings => DmaStreamTestConfig(
@@ -146,6 +186,7 @@ class WithDmaStreamTest extends Config(
 
 class WithNastiConverterTest extends Config(
   (pname, site, here) => pname match {
+    case GroundTestUncachedClients => 1
     case BuildGroundTest =>
       (id: Int, p: Parameters) => Module(new NastiConverterTest()(p))
     case _ => throw new CDEMatchError
@@ -160,15 +201,18 @@ class WithUnitTest extends Config(
 
 class WithTraceGen extends Config(
   (pname, site, here) => pname match {
+    case GroundTestCachedClients => 1
     case BuildGroundTest =>
       (id: Int, p: Parameters) => Module(new GroundTestTraceGenerator(id)(p))
-    case NGenerators => site(NTiles)
     case MaxGenerateRequests => 128
     case AddressBag => List(0x8, 0x10, 0x108, 0x100008)
     case _ => throw new CDEMatchError
   })
 
 class ComparatorConfig extends Config(new WithComparator ++ new BaseConfig)
+class ComparatorL2Config extends Config(
+  new WithAtomics ++ new WithPrefetches ++
+  new WithL2Cache ++ new ComparatorConfig)
 class GroundTestConfig extends Config(new WithGroundTest ++ new BaseConfig)
 class MemtestConfig extends Config(new WithMemtest ++ new GroundTestConfig)
 class MemtestL2Config extends Config(
@@ -183,8 +227,22 @@ class DmaTestConfig extends Config(new WithDmaTest ++ new WithL2Cache ++ new Gro
 class DmaStreamTestConfig extends Config(new WithDmaStreamTest ++ new WithStreamLoopback ++ new WithL2Cache ++ new GroundTestConfig)
 class NastiConverterTestConfig extends Config(new WithNastiConverterTest ++ new GroundTestConfig)
 class UnitTestConfig extends Config(new WithUnitTest ++ new GroundTestConfig)
-class TraceGenConfig extends Config(new With2Cores ++ new WithL2Cache ++ new WithTraceGen ++ new GroundTestConfig)
+class TraceGenConfig extends Config(new WithNCores(2) ++ new WithL2Cache ++ new WithTraceGen ++ new GroundTestConfig)
+
+class WithNCachedGenerators(n: Int) extends Config(
+  (pname, site, here) => pname match {
+    case GroundTestCachedClients => n
+    case _ => throw new CDEMatchError
+  })
+
+class WithNUncachedGenerators(n: Int) extends Config(
+  (pname, site, here) => pname match {
+    case GroundTestUncachedClients => n
+    case _ => throw new CDEMatchError
+  })
 
 class FancyMemtestConfig extends Config(
-  new With2Cores ++ new With2MemoryChannels ++ new With4BanksPerMemChannel ++
+  new WithNCachedGenerators(1) ++ new WithNUncachedGenerators(2) ++
+  new WithNCores(2) ++
+  new WithNMemoryChannels(2) ++ new WithNBanksPerMemChannel(4) ++
   new WithMemtest ++ new WithL2Cache ++ new GroundTestConfig)
diff --git a/uncore b/uncore
index 446ca034..49bcc44f 160000
--- a/uncore
+++ b/uncore
@@ -1 +1 @@
-Subproject commit 446ca034b2840f3a3ce35d4390859435d4adb9b4
+Subproject commit 49bcc44fcfdfa5b6cd9ddcffc1443164d4009622
diff --git a/vsrc/rocketTestHarness.v b/vsrc/rocketTestHarness.v
index 26e0e1ce..482df725 100644
--- a/vsrc/rocketTestHarness.v
+++ b/vsrc/rocketTestHarness.v
@@ -170,6 +170,8 @@ module rocketTestHarness;
 
     if (exit == 1)
     begin
+      if (verbose)
+        $fdisplay(stderr, "Completed after %d simulation cycles", trace_count);
       `VCDPLUSCLOSE
       htif_fini(1'b0);
     end