riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Clean up TileLinkRecursiveInterconnect a bit

Browse Source
This commit is contained in:
Andrew Waterman 2016-04-27 14:53:11 -07:00
parent 87cecc336f
commit 81ff127dc3
1 changed files with 15 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

38
uncore/src/main/scala/interconnect.scala
View File

@ -257,27 +257,25 @@ abstract class TileLinkInterconnect(implicit p: Parameters) extends TLModule()(p
} }
class TileLinkRecursiveInterconnect( class TileLinkRecursiveInterconnect(
val nInner: Int, val nOuter: Int, val nInner: Int, addrmap: AddrMap, base: BigInt)
addrmap: AddrMap, base: BigInt)
(implicit p: Parameters) extends TileLinkInterconnect()(p) { (implicit p: Parameters) extends TileLinkInterconnect()(p) {
var lastEnd = base var lastEnd = base
var outInd = 0
val levelSize = addrmap.size val levelSize = addrmap.size
val realAddrMap = new ArraySeq[(BigInt, BigInt)](addrmap.size) val nOuter = addrmap.countSlaves
addrmap.zipWithIndex.foreach { case (AddrMapEntry(name, startOpt, region), i) => val realAddrMap = addrmap map { case AddrMapEntry(name, region) =>
val start = startOpt.getOrElse(lastEnd) val start = lastEnd
val size = region.size val size = region.size
require(bigIntPow2(size), require(isPow2(size),
s"Region $name size $size is not a power of 2") s"Region $name size $size is not a power of 2")
require(start % size == 0, require(start % size == 0,
f"Region $name start address 0x$start%x not divisible by 0x$size%x" ) f"Region $name start address 0x$start%x not divisible by 0x$size%x" )
require(start >= lastEnd, require(start >= lastEnd,
f"Region $name start address 0x$start%x before previous region end") f"Region $name start address 0x$start%x before previous region end")
realAddrMap(i) = (start, size)
lastEnd = start + size lastEnd = start + size
(start, size)
} }
val routeSel = (addr: UInt) => { val routeSel = (addr: UInt) => {
@ -289,25 +287,19 @@ class TileLinkRecursiveInterconnect(
val xbar = Module(new ClientUncachedTileLinkIOCrossbar(nInner, levelSize, routeSel)) val xbar = Module(new ClientUncachedTileLinkIOCrossbar(nInner, levelSize, routeSel))
xbar.io.in <> io.in xbar.io.in <> io.in
addrmap.zip(realAddrMap).zip(xbar.io.out).zipWithIndex.foreach { io.out <> addrmap.zip(realAddrMap).zip(xbar.io.out).zipWithIndex.flatMap {
case (((entry, (start, size)), xbarOut), i) => { case (((entry, (start, size)), xbarOut), i) => {
entry.region match { entry.region match {
case MemSize(_, _, _) => case MemSize(_, _, _) =>
io.out(outInd) <> xbarOut Some(xbarOut)
outInd += 1 case MemSubmap(_, submap) if submap.isEmpty =>
xbarOut.acquire.ready := Bool(false)
xbarOut.grant.valid := Bool(false)
None
case MemSubmap(_, submap) => case MemSubmap(_, submap) =>
if (submap.isEmpty) { val ic = Module(new TileLinkRecursiveInterconnect(1, submap, start))
xbarOut.acquire.ready := Bool(false) ic.io.in.head <> xbarOut
xbarOut.grant.valid := Bool(false) ic.io.out
} else {
val subSlaves = submap.countSlaves
val outputs = io.out.drop(outInd).take(subSlaves)
val ic = Module(new TileLinkRecursiveInterconnect(1, subSlaves, submap, start))
ic.io.in.head <> xbarOut
for ((o, s) <- outputs zip ic.io.out)
o <> s
outInd += subSlaves
}
} }
} }
} }