Clean up TileLinkRecursiveInterconnect a bit
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@ -257,27 +257,25 @@ abstract class TileLinkInterconnect(implicit p: Parameters) extends TLModule()(p
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}
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}
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class TileLinkRecursiveInterconnect(
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class TileLinkRecursiveInterconnect(
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val nInner: Int, val nOuter: Int,
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val nInner: Int, addrmap: AddrMap, base: BigInt)
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addrmap: AddrMap, base: BigInt)
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(implicit p: Parameters) extends TileLinkInterconnect()(p) {
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(implicit p: Parameters) extends TileLinkInterconnect()(p) {
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var lastEnd = base
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var lastEnd = base
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var outInd = 0
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val levelSize = addrmap.size
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val levelSize = addrmap.size
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val realAddrMap = new ArraySeq[(BigInt, BigInt)](addrmap.size)
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val nOuter = addrmap.countSlaves
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addrmap.zipWithIndex.foreach { case (AddrMapEntry(name, startOpt, region), i) =>
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val realAddrMap = addrmap map { case AddrMapEntry(name, region) =>
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val start = startOpt.getOrElse(lastEnd)
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val start = lastEnd
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val size = region.size
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val size = region.size
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require(bigIntPow2(size),
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require(isPow2(size),
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s"Region $name size $size is not a power of 2")
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s"Region $name size $size is not a power of 2")
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require(start % size == 0,
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require(start % size == 0,
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f"Region $name start address 0x$start%x not divisible by 0x$size%x" )
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f"Region $name start address 0x$start%x not divisible by 0x$size%x" )
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require(start >= lastEnd,
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require(start >= lastEnd,
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f"Region $name start address 0x$start%x before previous region end")
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f"Region $name start address 0x$start%x before previous region end")
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realAddrMap(i) = (start, size)
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lastEnd = start + size
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lastEnd = start + size
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(start, size)
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}
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}
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val routeSel = (addr: UInt) => {
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val routeSel = (addr: UInt) => {
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@ -289,25 +287,19 @@ class TileLinkRecursiveInterconnect(
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val xbar = Module(new ClientUncachedTileLinkIOCrossbar(nInner, levelSize, routeSel))
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val xbar = Module(new ClientUncachedTileLinkIOCrossbar(nInner, levelSize, routeSel))
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xbar.io.in <> io.in
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xbar.io.in <> io.in
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addrmap.zip(realAddrMap).zip(xbar.io.out).zipWithIndex.foreach {
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io.out <> addrmap.zip(realAddrMap).zip(xbar.io.out).zipWithIndex.flatMap {
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case (((entry, (start, size)), xbarOut), i) => {
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case (((entry, (start, size)), xbarOut), i) => {
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entry.region match {
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entry.region match {
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case MemSize(_, _, _) =>
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case MemSize(_, _, _) =>
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io.out(outInd) <> xbarOut
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Some(xbarOut)
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outInd += 1
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case MemSubmap(_, submap) if submap.isEmpty =>
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case MemSubmap(_, submap) =>
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if (submap.isEmpty) {
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xbarOut.acquire.ready := Bool(false)
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xbarOut.acquire.ready := Bool(false)
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xbarOut.grant.valid := Bool(false)
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xbarOut.grant.valid := Bool(false)
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} else {
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None
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val subSlaves = submap.countSlaves
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case MemSubmap(_, submap) =>
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val outputs = io.out.drop(outInd).take(subSlaves)
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val ic = Module(new TileLinkRecursiveInterconnect(1, submap, start))
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val ic = Module(new TileLinkRecursiveInterconnect(1, subSlaves, submap, start))
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ic.io.in.head <> xbarOut
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ic.io.in.head <> xbarOut
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for ((o, s) <- outputs zip ic.io.out)
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ic.io.out
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o <> s
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outInd += subSlaves
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}
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}
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}
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}
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}
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}
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}
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