riscv/rocket-chip
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coreplex: guarantee FIFO for those tiles that need it

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This commit is contained in:
Wesley W. Terpstra 2017-03-20 18:52:03 -07:00
parent 198afddb4b
commit 81d717e82f
2 changed files with 12 additions and 4 deletions
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12
src/main/scala/coreplex/RocketTiles.scala
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@ -47,8 +47,10 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
case Synchronous => { case Synchronous => {
val tile = LazyModule(new RocketTile(c, i)(pWithExtra)) val tile = LazyModule(new RocketTile(c, i)(pWithExtra))
val buffer = LazyModule(new TLBuffer) val buffer = LazyModule(new TLBuffer)
val fixer = LazyModule(new TLFIFOFixer)
buffer.node :=* tile.masterNode buffer.node :=* tile.masterNode
l1tol2.node :=* buffer.node fixer.node :=* buffer.node
l1tol2.node :=* fixer.node
tile.slaveNode :*= cbus.node tile.slaveNode :*= cbus.node
tile.intNode := intBar.intnode tile.intNode := intBar.intnode
(io: HasRocketTilesBundle) => { (io: HasRocketTilesBundle) => {
@ -62,8 +64,10 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
val wrapper = LazyModule(new AsyncRocketTile(c, i)(pWithExtra)) val wrapper = LazyModule(new AsyncRocketTile(c, i)(pWithExtra))
val sink = LazyModule(new TLAsyncCrossingSink(depth, sync)) val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
val source = LazyModule(new TLAsyncCrossingSource(sync)) val source = LazyModule(new TLAsyncCrossingSource(sync))
val fixer = LazyModule(new TLFIFOFixer)
sink.node :=* wrapper.masterNode sink.node :=* wrapper.masterNode
l1tol2.node :=* sink.node fixer.node :=* sink.node
l1tol2.node :=* fixer.node
wrapper.slaveNode :*= source.node wrapper.slaveNode :*= source.node
wrapper.intNode := intBar.intnode wrapper.intNode := intBar.intnode
source.node :*= cbus.node source.node :*= cbus.node
@ -79,8 +83,10 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
val wrapper = LazyModule(new RationalRocketTile(c, i)(pWithExtra)) val wrapper = LazyModule(new RationalRocketTile(c, i)(pWithExtra))
val sink = LazyModule(new TLRationalCrossingSink(util.FastToSlow)) val sink = LazyModule(new TLRationalCrossingSink(util.FastToSlow))
val source = LazyModule(new TLRationalCrossingSource) val source = LazyModule(new TLRationalCrossingSource)
val fixer = LazyModule(new TLFIFOFixer)
sink.node :=* wrapper.masterNode sink.node :=* wrapper.masterNode
l1tol2.node :=* sink.node fixer.node :=* sink.node
l1tol2.node :=* fixer.node
wrapper.slaveNode :*= source.node wrapper.slaveNode :*= source.node
wrapper.intNode := intBar.intnode wrapper.intNode := intBar.intnode
source.node :*= cbus.node source.node :*= cbus.node

4
src/main/scala/groundtest/Coreplex.scala
View File

@ -40,7 +40,9 @@ class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex {
}})) }}))
} }
tiles.foreach { l1tol2.node :=* _.masterNode } val fixer = LazyModule(new TLFIFOFixer)
l1tol2.node :=* fixer.node
tiles.foreach { fixer.node :=* _.masterNode }
val cbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), false, cbus_beatBytes)) val cbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), false, cbus_beatBytes))
cbusRAM.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node) cbusRAM.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node)