From 81d717e82f6b37f439e15a8136ad996ec61b4719 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Mon, 20 Mar 2017 18:52:03 -0700
Subject: [PATCH] coreplex: guarantee FIFO for those tiles that need it

---
 src/main/scala/coreplex/RocketTiles.scala | 12 +++++++++---
 src/main/scala/groundtest/Coreplex.scala  |  4 +++-
 2 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/src/main/scala/coreplex/RocketTiles.scala b/src/main/scala/coreplex/RocketTiles.scala
index 0ee07d79..7f7493e2 100644
--- a/src/main/scala/coreplex/RocketTiles.scala
+++ b/src/main/scala/coreplex/RocketTiles.scala
@@ -47,8 +47,10 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
       case Synchronous => {
         val tile = LazyModule(new RocketTile(c, i)(pWithExtra))
         val buffer = LazyModule(new TLBuffer)
+        val fixer = LazyModule(new TLFIFOFixer)
         buffer.node :=* tile.masterNode
-        l1tol2.node :=* buffer.node
+        fixer.node :=* buffer.node
+        l1tol2.node :=* fixer.node
         tile.slaveNode :*= cbus.node
         tile.intNode := intBar.intnode
         (io: HasRocketTilesBundle) => {
@@ -62,8 +64,10 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
         val wrapper = LazyModule(new AsyncRocketTile(c, i)(pWithExtra))
         val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))
         val source = LazyModule(new TLAsyncCrossingSource(sync))
+        val fixer = LazyModule(new TLFIFOFixer)
         sink.node :=* wrapper.masterNode
-        l1tol2.node :=* sink.node
+        fixer.node :=* sink.node
+        l1tol2.node :=* fixer.node
         wrapper.slaveNode :*= source.node
         wrapper.intNode := intBar.intnode
         source.node :*= cbus.node
@@ -79,8 +83,10 @@ trait HasRocketTiles extends CoreplexRISCVPlatform {
         val wrapper = LazyModule(new RationalRocketTile(c, i)(pWithExtra))
         val sink = LazyModule(new TLRationalCrossingSink(util.FastToSlow))
         val source = LazyModule(new TLRationalCrossingSource)
+        val fixer = LazyModule(new TLFIFOFixer)
         sink.node :=* wrapper.masterNode
-        l1tol2.node :=* sink.node
+        fixer.node :=* sink.node
+        l1tol2.node :=* fixer.node
         wrapper.slaveNode :*= source.node
         wrapper.intNode := intBar.intnode
         source.node :*= cbus.node
diff --git a/src/main/scala/groundtest/Coreplex.scala b/src/main/scala/groundtest/Coreplex.scala
index fb0b8756..60848787 100644
--- a/src/main/scala/groundtest/Coreplex.scala
+++ b/src/main/scala/groundtest/Coreplex.scala
@@ -40,7 +40,9 @@ class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex {
     }}))
   }
 
-  tiles.foreach { l1tol2.node :=* _.masterNode }
+  val fixer = LazyModule(new TLFIFOFixer)
+  l1tol2.node :=* fixer.node
+  tiles.foreach { fixer.node :=* _.masterNode }
 
   val cbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), false, cbus_beatBytes))
   cbusRAM.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node)