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coreplex: guarantee FIFO for those tiles that need it

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This commit is contained in:
Wesley W. Terpstra
2017-03-20 18:52:03 -07:00
parent 198afddb4b
commit 81d717e82f
2 changed files with 12 additions and 4 deletions
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4
src/main/scala/groundtest/Coreplex.scala
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@ -40,7 +40,9 @@ class GroundTestCoreplex(implicit p: Parameters) extends BaseCoreplex {
}}))
}
tiles.foreach { l1tol2.node :=* _.masterNode }
val fixer = LazyModule(new TLFIFOFixer)
l1tol2.node :=* fixer.node
tiles.foreach { fixer.node :=* _.masterNode }
val cbusRAM = LazyModule(new TLRAM(AddressSet(testRamAddr, 0xffff), false, cbus_beatBytes))
cbusRAM.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node)