riscv/rocket-chip
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implement DMA unit

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This commit is contained in:
Howard Mao 2015-11-17 18:21:52 -08:00
parent 1a272677ca
commit 8190bf6e18
6 changed files with 69 additions and 12 deletions
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2
groundtest

@ -1 +1 @@
Subproject commit 49a2e33ad9a91d3dbf58b0342b43d4e60db87104
Subproject commit bcfebe0e0ecb91f6af8808ac60b0efcbdf5d44cf

2
rocket

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Subproject commit b08f86b4fb9ef44d27ddda1b038e0d1cc15f0b24
Subproject commit 709f35ff1d0b8482d70427c9a455a5a3863d0f4c

29
src/main/scala/Configs.scala
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@ -142,6 +142,10 @@ class DefaultConfig extends Config (
}
case BuildRoCC => Nil
case RoccNMemChannels => site(BuildRoCC).map(_.nMemChannels).foldLeft(0)(_ + _)
case UseDma => false
case NDmaTransactors => 3
case NDmaClients => site(NTiles)
case NDmaXactsPerClient => site(NDmaTransactors)
//Rocket Core Constants
case FetchWidth => 1
case RetireWidth => 1
@ -173,11 +177,15 @@ class DefaultConfig extends Config (
coherencePolicy = new MESICoherence(site(L2DirectoryRepresentation)),
nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels),
nCachingClients = site(NTiles),
nCachelessClients = 1 + site(NTiles) *
(1 + (if(site(BuildRoCC).isEmpty) 0 else site(RoccNMemChannels))),
nCachelessClients = (if (site(UseDma)) 2 else 1) +
site(NTiles) *
(1 + (if(site(BuildRoCC).isEmpty) 0
else site(RoccNMemChannels))),
maxClientXacts = max(site(NMSHRs) + site(NIOMSHRs),
if(site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts)),
maxClientsPerPort = if(site(BuildRoCC).isEmpty) 1 else 2,
max(if (site(BuildRoCC).isEmpty) 1 else site(RoccMaxTaggedMemXacts),
if (site(UseDma)) 4 else 1)),
maxClientsPerPort = max(if (site(BuildRoCC).isEmpty) 1 else 2,
if (site(UseDma)) site(NDmaTransactors) else 1),
maxManagerXacts = site(NAcquireTransactors) + 2,
dataBits = site(CacheBlockBytes)*8)
case TLKey("L2toMC") =>
@ -365,6 +373,19 @@ class WithRoccExample extends Config(
class RoccExampleConfig extends Config(new WithRoccExample ++ new DefaultConfig)
class WithDmaController extends Config(
(pname, site, here) => pname match {
case UseDma => true
case BuildRoCC => Seq(
RoccParameters(
opcodes = OpcodeSet.custom2,
generator = (p: Parameters) => Module(new DmaController()(p)),
useDma = true))
case RoccMaxTaggedMemXacts => 1
})
class DmaControllerConfig extends Config(new WithDmaController ++ new DefaultL2Config)
class SmallL2Config extends Config(
new With2MemoryChannels ++ new With4BanksPerMemChannel ++
new WithL2Capacity256 ++ new DefaultL2Config)

21
src/main/scala/RocketChip.scala
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@ -29,13 +29,17 @@ case object BuildL2CoherenceManager extends Field[(Int, Parameters) => Coherence
case object BuildTiles extends Field[Seq[(Bool, Parameters) => Tile]]
/** Start address of the "io" region in the memory map */
case object ExternalIOStart extends Field[BigInt]
/** Enable DMA engine */
case object UseDma extends Field[Boolean]
/** Utility trait for quick access to some relevant parameters */
trait HasTopLevelParameters {
implicit val p: Parameters
lazy val useDma = p(UseDma)
lazy val nTiles = p(NTiles)
lazy val nCachedTilePorts = p(TLKey("L1toL2")).nCachingClients
lazy val nUncachedTilePorts = p(TLKey("L1toL2")).nCachelessClients - 1
lazy val nUncachedTilePorts =
p(TLKey("L1toL2")).nCachelessClients - (if (useDma) 2 else 1)
lazy val htifW = p(HtifKey).width
lazy val csrAddrBits = 12
lazy val nMemChannels = p(NMemoryChannels)
@ -109,6 +113,7 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
uncore.io.tiles_uncached <> tileList.map(_.io.uncached).flatten
io.host <> uncore.io.host
if (p(UseBackupMemoryPort)) { io.mem_backup_ctrl <> uncore.io.mem_backup_ctrl }
if (p(UseDma)) { uncore.io.dma <> tileList.map(_.io.dma) }
io.mem.zip(uncore.io.mem).foreach { case (outer, inner) =>
TopUtils.connectNasti(outer, inner)
@ -137,6 +142,7 @@ class Uncore(implicit val p: Parameters) extends Module
val htif = Vec(new HtifIO, nTiles).flip
val mem_backup_ctrl = new MemBackupCtrlIO
val mmio = new NastiIO
val dma = Vec(nTiles, new DmaIO).flip
}
val htif = Module(new Htif(CSRs.mreset)) // One HTIF module per chip
@ -145,6 +151,11 @@ class Uncore(implicit val p: Parameters) extends Module
outmemsys.io.htif_uncached <> htif.io.mem
outmemsys.io.tiles_uncached <> io.tiles_uncached
outmemsys.io.tiles_cached <> io.tiles_cached
if (p(UseDma)) {
val dma_arb = Module(new DmaArbiter(nTiles))
dma_arb.io.in <> io.dma
outmemsys.io.dma <> dma_arb.io.out
}
for (i <- 0 until nTiles) {
io.htif(i).reset := htif.io.cpu(i).reset
@ -198,12 +209,18 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
val scr = new SMIIO(xLen, scrAddrBits)
val mmio = new NastiIO
val deviceTree = new NastiIO
val dma = (new DmaIO).flip
}
val dmaOpt = if (p(UseDma)) Some(Module(new DmaEngine)) else None
dmaOpt.foreach { dma => dma.io.dma <> io.dma }
// Create a simple L1toL2 NoC between the tiles+htif and the banks of outer memory
// Cached ports are first in client list, making sharerToClientId just an indentity function
// addrToBank is sed to hash physical addresses (of cache blocks) to banks (and thereby memory channels)
val ordered_clients = (io.tiles_cached ++ (io.tiles_uncached :+ io.htif_uncached).map(TileLinkIOWrapper(_)))
val ordered_clients = (io.tiles_cached ++
(io.tiles_uncached ++ dmaOpt.map(_.io.mem) :+ io.htif_uncached)
.map(TileLinkIOWrapper(_)))
def sharerToClientId(sharerId: UInt) = sharerId
def addrToBank(addr: Bits): UInt = if(nBanks > 1) addr(lsb + log2Up(nBanks) - 1, lsb) else UInt(0)
val preBuffering = TileLinkDepths(2,2,2,2,2)

25
src/main/scala/TestConfigs.scala
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@ -14,10 +14,12 @@ class WithGroundTest extends Config(
coherencePolicy = new MESICoherence(site(L2DirectoryRepresentation)),
nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels),
nCachingClients = site(NTiles),
nCachelessClients = site(NTiles) + 1,
nCachelessClients = site(NTiles) + (if (site(UseDma)) 2 else 1),
maxClientXacts = max(site(NMSHRs) + site(NIOMSHRs),
site(GroundTestMaxXacts)),
maxClientsPerPort = 1,
max(site(GroundTestMaxXacts),
if (site(UseDma)) 4 else 1)),
maxClientsPerPort = max(if (site(BuildRoCC).isEmpty) 1 else 2,
if (site(UseDma)) site(NDmaTransactors) else 1),
maxManagerXacts = site(NAcquireTransactors) + 2,
dataBits = site(CacheBlockBytes)*8)
case BuildTiles => {
@ -69,6 +71,22 @@ class WithCacheRegressionTest extends Config(
case GroundTestMaxXacts => 3
})
class WithDmaTest extends Config(
(pname, site, here) => pname match {
case UseDma => true
case BuildGroundTest =>
(id: Int, p: Parameters) => Module(new DmaTest()(p))
case DmaTestSet => DmaTestCases(
(0x00001FF0, 0x00002FF4, 72),
(0x00001FF4, 0x00002FF0, 72),
(0x00001FF0, 0x00002FE0, 72),
(0x00001FE0, 0x00002FF0, 72),
(0x00884DA4, 0x008836C0, 40),
(0x00800008, 0x00800008, 64))
case DmaTestDataStart => 0x3012CC00
case DmaTestDataStride => 8
})
class GroundTestConfig extends Config(new WithGroundTest ++ new DefaultConfig)
class MemtestConfig extends Config(new WithMemtest ++ new GroundTestConfig)
class MemtestL2Config extends Config(
@ -79,6 +97,7 @@ class BroadcastRegressionTestConfig extends Config(
new WithBroadcastRegressionTest ++ new GroundTestConfig)
class CacheRegressionTestConfig extends Config(
new WithCacheRegressionTest ++ new WithL2Cache ++ new GroundTestConfig)
class DmaTestConfig extends Config(new WithDmaTest ++ new WithL2Cache ++ new GroundTestConfig)
class FancyMemtestConfig extends Config(
new With2Cores ++ new With2MemoryChannels ++ new With2BanksPerMemChannel ++

2
uncore

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Subproject commit 3bb143cc36fba3433b0ceb4256ea11a8a00155ea
Subproject commit 30058958457f718718338b2a2f71b39df848a8c5