riscv/rocket-chip
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added HasAddrMapParameters

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This commit is contained in:
Henry Cook
2015-10-06 18:20:19 -07:00
parent 84576650b5
commit 8173695800
3 changed files with 3 additions and 12 deletions
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2
rocket/src/main/scala/btb.scala
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@@ -10,7 +10,7 @@ case object BtbKey extends Field[BtbParameters]
case class BtbParameters(nEntries: Int = 62, nRAS: Int = 2, updatesOutOfOrder: Boolean = false)
abstract trait HasBtbParameters extends HasCoreParameters {
val matchBits = p(PgIdxBits)
val matchBits = pgIdxBits
val entries = p(BtbKey).nEntries
val nRAS = p(BtbKey).nRAS
val updatesOutOfOrder = p(BtbKey).updatesOutOfOrder

10
rocket/src/main/scala/rocket.scala
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@@ -22,17 +22,9 @@ case object CoreDataBits extends Field[Int]
case object CoreDCacheReqTagBits extends Field[Int]
case object NCustomMRWCSRs extends Field[Int]
trait HasCoreParameters {
trait HasCoreParameters extends HasAddrMapParameters {
implicit val p: Parameters
val xLen = p(XLen)
val paddrBits = p(PAddrBits)
val vaddrBits = p(VAddrBits)
val pgIdxBits = p(PgIdxBits)
val ppnBits = p(PPNBits)
val vpnBits = p(VPNBits)
val pgLevels = p(PgLevels)
val pgLevelBits = p(PgLevelBits)
val asIdBits = p(ASIdBits)
val retireWidth = p(RetireWidth)
val fetchWidth = p(FetchWidth)

3
rocket/src/main/scala/tlb.scala
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@@ -9,8 +9,7 @@ import scala.math._
case object NTLBEntries extends Field[Int]
trait HasTLBParameters extends HasCoreParameters {
val addrMap = new AddrHashMap(p(NastiAddrMap))
trait HasTLBParameters extends HasAddrMapParameters {
val entries = p(NTLBEntries)
val camAddrBits = ceil(log(entries)/log(2)).toInt
val camTagBits = asIdBits + vpnBits